3D vertical memory array cell structures and processes
Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a cell structure includes a word line, a selector layer, and a memory layer. The word line, the selector layer, and the memory layer form a vertical cell structure in which at least one of the selector layer and the memory layer are segmented to form a segment that blocks sneak path leakage current on the word line.
1. A method for forming a vertical memory structure, comprising:
forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.
2. The method of claim 1 , wherein the depositing of the selector material comprises:
removing portions of the word line layers from the internal surfaces of the word lines to form internal open regions; and
filling the internal open regions with the selector material to form the segments of the selector material.
3. The method of claim 1 , wherein the depositing of the memory material comprises depositing the memory material to form segments of the memory material, and wherein each segment of the memory material is deposited on a respective segment of the selector material.
4. A 3D vertical array that includes a plurality of cell structures that block sneak path leakage current, the cell structures formed by performing the operations of:
forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.
5. The array of claim 4 , wherein the depositing of the selector material comprises:
removing portions of the word line layers from the internal surfaces of the word lines to form internal open regions; and
filling the internal open regions with the selector material to form the segments of the selector material.
6. The array of claim 4 , wherein the depositing of the memory material comprises depositing the memory material to form segments of the memory material, and wherein each segment of the memory material is deposited on a respective segment of the selector material.