Devices including a passive material between memory cells and conductive access lines, and related electronic devices
A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.
1. A device, comprising:
memory cells disposed at an intersection between first conductive lines and second conductive lines, the memory cells comprising a chalcogenide material between a pair of electrodes; and
a passive material extending along the first conductive lines and exhibiting an electrical conductivity less than an electrical conductivity of the first conductive lines, the passive material spaced from the first conductive lines by a semimetal material.
2. The device of claim 1 , wherein the passive material is selected from the group consisting of aluminum oxide, tungsten silicon nitride, titanium silicon nitride, a metal nitride, silicon nitride, a metal silicide, and combinations thereof.
3. The device of claim 1 , wherein the passive material comprises aluminum oxide or tungsten silicon nitride.
4. The device of claim 1 , wherein the passive material exhibits a non-linear resistance responsive to exposure to changes in an electric field to which the passive material is exposed.
5. The device of claim 1 , wherein the first conductive lines comprise one or more of aluminum, copper, nickel, chromium, cobalt, ruthenium, rhodium, palladium, silver, platinum, gold, iridium, tantalum, tungsten, a conductive metal nitride, and a conductive metal silicide.
6. The device of claim 1 , wherein each memory cell further comprises an interfacial material comprising tungsten between one of the electrodes of the pair of electrodes and the chalcogenide material.
7. An electronic device, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device, the memory device comprising:
an array of memory cells, at least one memory cell of the array of memory cells comprising a memory material comprising a chalcogenide material;
a first conductive line contacting a first number of memory cells of the array of memory cells including the at least one memory cell;
a second conductive line contacting a second number of memory cells of the array of memory cells including the at least one memory cell;
a dielectric material adjacent the first conductive line and the first number of memory cells; and
a semimetal material adjacent to and overlying the dielectric material.
8. The electronic device of claim 7 , wherein the at least one memory cell further comprises aluminum oxide adjacent the chalcogenide material.
9. The electronic device of claim 7 , wherein the dielectric material comprises aluminum oxide.
10. The electronic device of claim 7 , wherein the semimetal material is coextensive with the dielectric material and the first conductive line.
11. A device, comprising:
a first conductive line extending in a first direction;
a second conductive line extending in a second direction substantially perpendicular to the first conductive line;
a memory cell between the first conductive line and the second conductive line, the memory cell comprising a memory material between a first electrode and a second electrode;
a passive material extending adjacent to the first conductive line and between the first conductive line and the memory cell; and
a semimetal material adjacent to and overlying the passive material.
12. The device of claim 11 , further comprising an additional passive material extending adjacent to the second conductive line and between the second conductive line and the memory cell.
13. The device of claim 11 , wherein the passive material exhibits an electrical conductivity less than an electrical conductivity of the first conductive line.
14. The device of claim 1 , further comprising an additional passive material extending along the second conductive lines.
15. The device of claim 14 , wherein the additional passive material extends substantially perpendicular to the passive material.
16. The device of claim 1 , wherein a thickness of the passive material is within a range of from about 0.5 nm to about 10 nm.
17. The device of claim 1 , wherein the semimetal material comprises a metal silicide.
18. The device of claim 1 , wherein a thickness of the semimetal material is greater than a thickness of the passive material.