Semiconductor memory device with a memory cell block including a block film
A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
1. A semiconductor memory device, comprising, in the case that three mutually intersecting directions are assumed to be an X direction, a Y direction, and a Z direction:
a semiconductor substrate having as principal plane a plane extending in the X direction and the Y direction; and
a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays aligned in the Y direction, each of the memory cell arrays including a plurality of column lines extending in the Z direction and arranged in the X direction, a plurality of row lines extending in the X direction and arranged in the Z direction, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines,
each of the memory cells including a variable resistance element having a transition metal oxide as a material,
at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material,
the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line, and
the block film configured from silicon nitride, silicon oxynitride, or silicon oxide.
2. The semiconductor memory device according to claim 1 , wherein
the variable resistance element and the block film are formed continuously between the plurality of row lines arranged in the Z direction.
3. The semiconductor memory device according to claim 1 , wherein
the variable resistance element is configured from hafnium oxide.
4. The semiconductor memory device according to claim 1 , wherein
two of the memory cell arrays adjacent in the Y direction share the plurality of column lines or the plurality of row lines.
5. A semiconductor memory device, comprising, in the case that three mutually intersecting directions are assumed to be an X direction, a Y direction, and a Z direction:
a semiconductor substrate having as principal plane a plane extending in the X direction and the Y direction; and
a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays aligned in the Y direction, each of the memory cell arrays including a plurality of column lines extending in the Z direction and arranged in the X direction, a plurality of row lines extending in the X direction and arranged in the Z direction, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines,
each of the memory cells including a variable resistance element having a transition metal oxide as a material,
at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material,
the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line,
the memory cell block including selection elements formed at each of one ends of the plurality of column lines, and a plurality of global column lines extending in the Y direction and arranged in the X direction, and
a plurality of the column lines aligned in the Y direction being each connected to one of the global column lines via the respective selection elements.
6. The semiconductor memory device according to claim 5 , wherein
the memory cell block includes a plurality of selection element control wiring lines extending in the X direction and arranged in the Y direction, and
a plurality of the control elements aligned in the X direction are commonly controlled by one of the selection element control wiring lines.
7. The semiconductor memory device according to claim 5 , wherein
the plurality of selection elements each includes, stacked sequentially in the Z direction from the global column lines to the column lines, a source region configured from a first conductivity type semiconductor, a channel region configured from a second conductivity type semiconductor, and a drain region configured from the first conductivity type semiconductor.
8. A semiconductor memory device, comprising, in the case that three mutually intersecting directions are assumed to be an X direction, a Y direction, and a Z direction:
a semiconductor substrate having as principal plane a plane extending in the X direction and the Y direction; and
a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays aligned in the Y direction, each of the memory cell arrays including a plurality of column lines extending in the Z direction and arranged in the X direction, a plurality of row lines extending in the X direction and arranged in the Z direction, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines,
each of the memory cells including a variable resistance element having a transition metal oxide as a material,
at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material,
the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line, and
a plurality of even-numbered ones of the row lines aligned in the Y direction being commonly connected, and a plurality of odd-numbered ones of the row lines aligned in the Y direction being commonly connected.