Semiconductor memory device and manufacturing method of the same

1. A semiconductor memory device comprising:

a plurality of memory cell arrays each comprising a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure;

a first well formed in the semiconductor substrate and having a first conductivity type;

an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate;

a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type; and

a contact line electrically connected to the first well.

2. The device of claim 1 , further comprising a third well which is formed in a surface region of the first well in contact with a side surface of the element isolation insulating film, includes an upper surface connected to the contact line, and has the first conductivity type.

3. The device of claim 2 , wherein an end portion of the second well is offset from an end portion of the element isolation insulating film in contact with the third well.

4. The device of claim 1 , further comprising a first transistor which is disposed adjacent to the second well, comprises a well whose bottom surface is equal to the bottom surface of the first well, and has the second conductivity type.

5. The device of claim 4 , further comprising a second transistor disposed adjacent to the first transistor, making a CMOS circuit together with the first transistor, and having the first conductivity type.

6. The device of claim 5 , further comprising a capacitor which is disposed adjacent to the second transistor, includes a well whose bottom surface is leveled with the bottom surface of the first well, has the first conductivity type, and includes a gate insulating film as an insulator.

7. The device of claim 5 , wherein a bottom surface of the well of the second transistor is equal to that of the second well.

8. The device of claim 1 , wherein

the plurality of memory cell arrays comprise a plurality of MATs arranged in a memory cell area, and

the second well is formed within a range below one of the plurality of MATs.

9. The device of claim 8 , wherein the memory cell comprises:

a variable resistance element whose current path has one end connected to a bit line; and

a diode comprising a cathode connected to the other end of the current path of the variable resistance element, and an anode connected to a word line.

10. The device of claim 1 , wherein in impurity concentration profiles of the first well and the second well obtained in a direction of depth from the bottom of the element isolation insulating film,

the first well has a first peak of a concentration of the impurity having the first conductivity type, and

the second well has a second peak of a concentration of the impurity having the second conductivity type, and

a depth of the first peak is deeper than a depth of the second peak.

11. The device of claim 1 , which further comprises a third well formed in a surface region of the first well in contact with a side surface of the element isolation insulating film, including an upper surface connected to the contact line, and having the first conductivity type, and

in which an end portion of the second well is not offset from an end portion of the element isolation insulating film in contact with the third well, and a portion where the second well is not formed is formed below the third well.