Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers; a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer; a stacked structure formed over the plurality channel connection layers and the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked; a pair of channel layers, formed through the stacked structure and connected to each channel connection layer of the plurality of channel connection layers; and a memory layer interposed between each of the channel layers and each of the second gate electrode layers.
1. A memory device, comprising:
a plurality of channel connection layers formed over a substrate;
a first gate electrode layer surrounding side surfaces and top surfaces except for bottom surfaces of the plurality channel connection layers;
a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer;
a stacked structure formed over the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked;
a pair of channel layers connected to each channel connection layer of the plurality of channel connection layers through the stacked structure and the first gate electrode layer; and
a memory layer interposed between each of the channel layers and each of the second gate electrode layers and between each of the channel layers and the first gate electrode layer.
2. The memory device of claim 1 , where the first gate electrode layer is separated for each block.
3. The memory device of claim 1 , where the memory layer and the gate dielectric layer are formed of different materials.
4. The memory device of claim 1 , further comprising:
a slit positioned between the channel layers, the slit being formed through the plurality of second gate electrode layers.
5. A method for fabricating a memory device, the method comprising:
forming a plurality of channel connection layers over a substrate;
forming a gate dielectric layer on surfaces of each of the channel connection layers;
forming a first gate electrode layer surrounding side surfaces and top surfaces except for bottom surfaces of the plurality channel connection layers;
forming a stacked structure over the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality of second gate electrode layers, which are alternately stacked;
forming a pair of channel holes to expose each channel connection layer of the plurality of channel connection layers through the stacked structure and the first gate electrode layer; and
forming a memory layer and a channel layer on a sidewall of each channel hole of the pair of channel holes.
6. The method of claim 5 , where forming the gate dielectric layer comprises:
performing an oxidation process on the plurality of channel connection layers.
7. The method of claim 5 , where forming the first gate electrode layer comprises:
forming a conductive material over the substrate; and
etching the conductive material to separate the conductive material for each block.
8. The method of claim 5 , where memory layer and the gate dielectric layer are formed of different materials.
9. The method of claim 5 , further comprising:
forming, through the plurality of second gate electrodes, a slit positioned between the channel holes.
10. A method for fabricating a memory device, the method comprising:
forming a plurality of channel connection layers over a substrate;
forming a gate dielectric layer on surfaces of each of channel connection layers;
forming a first gate electrode layer surrounding side surfaces and top surfaces except for bottom surfaces of the plurality channel connection layers;
forming a stacked structure over the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality of sacrificial layers, which are alternately stacked;
forming a pair of channel holes to expose each channel connection layer of the plurality of channel connection layers through the stacked structure and the first gate electrode layer;
forming a channel layer on a sidewall of each channel hole of the pair of channel holes;
replacing the sacrificial layers with second gate electrode layers; and
forming a memory layer interposed between each of the channel layers and each of the second gate electrode layers.
11. The method of claim 10 , where forming the gate dielectric layer comprises:
oxidizing the plurality of channel connection layers.
12. The method of claim 10 , where forming the first gate electrode layer comprises:
forming a conductive material over the substrate; and
etching the conductive material to separate the conductive material for each block.
13. The method of claim 10 , where the memory layer and the gate dielectric layer are formed of different materials.
14. The method of claim 10 , where replacing the sacrificial layers comprises:
forming, through the plurality of sacrificial layers, a slit positioned between the channel holes;
removing the plurality of sacrificial layers exposed through the slit; and
burying a conductive material in spaces formed by the removal of the plurality of sacrificial layers.
15. The method of claim 14 , where forming the memory layer comprises:
forming the memory layer along the inner walls of the spaces from which the sacrificial layers were removed, after the removing the plurality of sacrificial layers and before the burying of the conductive material.
16. The method of claim 10 , where forming the memory layer comprises:
forming the memory layer on sidewalls of the channel holes before forming the channel layer.