Vertical and 3D memory devices and methods of manufacturing the same
A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.
1. A memory device, comprising:
a plurality of stacks of horizontal active lines that comprise portions of layers of material in a plurality of levels, the portions of the layers forming the horizontal active lines having sides defined by rows and columns of holes in an array of holes that penetrate the layers of material;
a buttress including a plurality of insulating posts extending vertically between horizontal active lines in the plurality of stacks, each insulating post in the plurality of insulating posts being disposed between and recessed away from perimeters of adjacent holes in two columns and two rows of the array;
a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines disposed between the rows of holes in the array of holes; and
a memory film between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices.
2. The memory device of claim 1 , wherein the horizontal active lines comprise semiconductor channel lines, and the vertical slices comprise conductive word lines which surround the horizontal active lines.
3. The memory device of claim 1 , wherein the memory film comprises a multilayer, dielectric charge trapping structure, the horizontal active lines comprise a semiconductor, and the vertical slices comprise a conductive material.
4. The memory device of claim 1 , wherein at least one of the horizontal active lines has a thickness in a vertical dimension different from that of at least another of the horizontal active lines in the same stack.
5. The memory device of claim 1 , wherein the horizontal active lines have opposing sides with undulating shapes more narrow near a center of the vertical slices than near edges of the vertical slices.
6. The memory device of claim 1 , wherein the horizontal active lines are silicon, and the memory film comprises a multilayer, dielectric charge trapping structure.
7. The memory device of claim 1 , wherein the plurality of horizontal active lines have rounded surfaces where they penetrate the plurality of vertical slices.
8. A memory device, comprising:
a horizontal active line that comprises portions of a layer of material having sides defined by rows and columns of holes in an array of holes that penetrate the layer of material;
a buttress including a plurality of insulating posts extending vertically from an upper surface of the horizontal active line, each insulating post in the plurality of insulating posts being disposed between and recessed away from perimeters of adjacent holes in two columns and two rows of the array;
a dielectric charge trapping structure surrounding the horizontal channel line; and
a gate all around the dielectric charge trapping structure and the horizontal channel line.
9. The memory device of claim 8 , wherein the horizontal active line has a rounded surface where it is surrounded by the dielectric charge trapping structure.
10. A memory device, comprising:
a 3D block of horizontal channel, vertical gate-all-around flash memory cells, wherein the 3D block comprises:
a plurality of stacks of horizontal NAND bit line strips that comprise portions of layers of semiconductor material in a plurality of levels, the portions of the layers forming the horizontal bit line strips having sides defined by rows and columns of holes in an array of holes that penetrate the layers of material;
a buttress including a plurality of insulating posts extending vertically between horizontal bit line strips in the plurality of stacks, each insulating post in the plurality of insulating posts being disposed between and recessed away from perimeters of adjacent holes in two columns and two rows of the array;
a plurality of vertical word line slices penetrated by, and surrounding, the horizontal NAND bit line strips, and disposed between the rows of holes in the array of holes; and
a dielectric charge trapping structure between the horizontal NAND bit line strips in the plurality of stacks and the vertical slices in the plurality of vertical word line slices.
11. The memory device of claim 10 , wherein at least one of the horizontal NAND bit line strips has a thickness in a vertical dimension different from that of at least another of the horizontal NAND bit line strips in the same stack.
12. The memory device of claim 10 , wherein the horizontal NAND bit line strips are silicon.
13. The memory device of claim 10 , wherein the plurality of horizontal NAND bit line strips have rounded surfaces where they penetrate the plurality of word line vertical slices.
14. The memory device of claim 10 , wherein the bit line strips have opposing sides with undulating shapes more narrow near a center of the vertical word line slices than near edges of the vertical word line slices.
15. A method for manufacturing a memory, comprising:
forming a plurality of stacks of horizontal active lines that comprise portions of layers of material in a plurality of levels, the portions of the layers forming the horizontal active lines having sides defined by rows and columns of holes in an array of holes that penetrate the layers of material;
forming a buttress including a plurality of insulating posts extending vertically between horizontal active lines in the plurality of stacks, each insulating post in the plurality of insulating posts being disposed between and recessed away from perimeters of adjacent holes in two columns and two rows of the array;
forming a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines disposed between the rows of holes in the array of holes; and
forming a memory film between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices.
16. The memory device of claim 1 , wherein the posts in the plurality of posts are disposed centrally in a diagonal direction on the portions of the layers between perimeters of adjacent holes in two columns and two rows of the array.
17. The memory device of claim 8 , wherein the posts in the plurality of posts are disposed centrally in a diagonal direction on the portions of the horizontal active line between perimeters of adjacent holes in two columns and two rows of the array.
18. The memory device of claim 8 , wherein the horizontal active line has opposing sides with undulating shapes more narrow near a center of the gate than near edges of the gate.
19. The memory device of claim 10 , wherein the posts in the plurality of posts are disposed centrally in a diagonal direction on the portions of the layers between perimeters of adjacent holes in two columns and two rows of the array.
20. The method of claim 15 , wherein the posts in the plurality of posts are disposed centrally in a diagonal direction on the portions of the layers between perimeters of adjacent holes in two columns and two rows of the array.