Three-dimensional (3D) semiconductor device
A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
1. A semiconductor device comprising:
interlayer dielectrics stacked and spaced apart from each other;
a channel layer passing through the interlayer dielectrics;
line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics;
a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer;
a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer;
a protection pattern filled in the first region on the reaction preventing pattern; and
a first metal layer filled in a second region of each of the line pattern regions.
2. The semiconductor device of claim 1 , wherein the reaction preventing pattern includes an oxide layer.
3. The semiconductor device of claim 1 , wherein the protection pattern has an etch selectivity with respect to the reaction preventing pattern and the barrier pattern.
4. The semiconductor device of claim 1 , wherein the protection pattern includes polysilicon.
5. The semiconductor device of claim 1 , wherein the first metal layer includes tungsten (W).
6. The semiconductor device of claim 1 , further comprising pad pattern regions connected to end portions of the line pattern regions and having a thickness greater than a thickness of the line pattern regions.
7. The semiconductor device of claim 6 , wherein the barrier pattern extends along a surface of each of the pad pattern regions.
8. The semiconductor device of claim 7 , wherein a thickness of the barrier pattern on the pad pattern regions is less than that of the barrier pattern on the line pattern regions.
9. The semiconductor device of claim 7 , further comprising:
an etch stop pattern formed along a surface of the barrier pattern on each of the pad pattern regions; and
a second metal layer filled in each of the pad pattern regions on the etch stop pattern.
10. The semiconductor device of claim 9 , wherein the etch stop pattern includes TiNSi x , where x is a natural number.
11. The semiconductor device of claim 9 , wherein the second metal layer includes tungsten (W).
12. The semiconductor device of claim 9 , wherein the second metal layer is filled in a portion of each of the pad pattern regions such that the pad pattern regions are opened by a predetermined width from edges of the pad pattern regions.