Memory device

1. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel;

forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and

forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first interlayer insulating layer disposed in the peripheral circuit region and covering a top and sides of the plurality of circuit elements, and a second interlayer insulating layer disposed on the first interlayer insulating layer,

wherein the first interlayer insulating layer is disposed between the second interlayer insulating layer and the substrate in the peripheral circuit region, and

wherein the first interlayer insulating layer is directly in contact with the second interlayer insulating layer, and an upper surface of the first interlayer insulating layer is at least higher than an upper surface of a second gate electrode layer secondly stacked on the substrate.

2. The method of claim 1 , wherein the first interlayer insulating layer is formed to extend continuously from at least one of the plurality of circuit elements at the peripheral circuit region into the cell region to extend above a top surface of at least one of the gate electrode layers.

3. The method of claim 2 , wherein the first interlayer insulating layer is formed to extend continuously from the channel on the uppermost gate electrode layer to at least one of the plurality of circuit elements at the peripheral circuit region.

4. The method of claim 1 , wherein a ratio of a thickness of the first interlayer insulating layer to a thickness of the second interlayer insulating layer at the peripheral circuit region is between 1:10 to 1:20.

5. The method of claim 1 , further comprising:

forming the plurality of gate electrode layers in a stack at the cell region of the substrate, such that lower gate electrode layers in the stack extend further in a direction toward the peripheral circuit region than higher gate electrode layers in the stack.

6. The method of claim 5 , wherein the gate electrode layers and insulating layers are stacked in a step-wise manner, and further comprising forming the first interlayer insulating layer to cover a plurality of steps of the gate electrode layer-insulating layer stack.

7. The method of claim 1 , wherein forming the plurality of circuit elements includes forming a plurality of horizontal transistors, and the first interlayer insulating layer fills spaces between transistors of the plurality of horizontal transistors.

8. A method of manufacturing an electronic device, the method comprising:

providing a substrate;

providing in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel;

providing a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and

providing an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first interlayer insulating layer covering the plurality of circuit elements, and a second interlayer insulating layer disposed on the first interlayer insulating layer,

wherein the first interlayer insulating layer is disposed between the second interlayer insulating layer and the substrate,

wherein the first interlayer insulating layer has better gap filling properties than the second interlayer insulating layer, and

wherein the second interlayer insulating layer has a higher deposition rate than the first interlayer insulating layer.

9. The method of claim 8 , wherein the first interlayer insulating layer includes a high density plasma (HDP) oxide layer, and the second interlayer insulating layer includes a tetra-ethyl-ortho-silicate (TEOS) oxide layer.

10. The method of claim 8 , wherein the first interlayer insulating layer extends continuously from at least a first circuit element of the plurality of circuit elements to at least a first portion of the plurality of gate electrode layers to cover at least the first circuit element and at least the first portion of the plurality of gate electrode layers.

11. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel;

forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and

forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first interlayer insulating layer disposed in the peripheral circuit region and covering the plurality of circuit elements, and a second interlayer insulating layer disposed on the first interlayer insulating layer,

wherein the first interlayer insulating layer is disposed between the second interlayer insulating layer and the substrate in the peripheral circuit region and fills a space between the plurality of circuit elements and an upper surface of the substrate, and

wherein the first interlayer insulating layer is formed to extend continuously from at least one of the plurality of circuit elements at the peripheral circuit region into the cell region to extend above a top surface of at least one of the gate electrode layers.

12. The method of claim 11 , wherein the first interlayer insulating layer is formed to extend continuously from the channel on the uppermost gate electrode layer to at least one of the plurality of circuit elements at the peripheral circuit region.

13. The method of claim 11 , wherein a ratio of a thickness of the first interlayer insulating layer to a thickness of the second interlayer insulating layer at the peripheral circuit region is between 1:10 to 1:20.

14. The method of claim 11 , further comprising:

forming the plurality of gate electrode layers in a stack at the cell region of the substrate, such that lower gate electrode layers in the stack extend further in a direction toward the peripheral circuit region than higher gate electrode layers in the stack.

15. The method of claim 14 , wherein the gate electrode layers and insulating layers are stacked in a step-wise manner, and further comprising forming the first interlayer insulating layer to cover a plurality of steps of the gate electrode layer-insulating layer stack.

16. The method of claim 11 , wherein forming the plurality of circuit elements includes forming a plurality of horizontal transistors, and the first interlayer insulating layer fills spaces between transistors of the plurality of horizontal transistors.