IP Library Granted Patent US 8,440,528
Granted Patent B2
US 8,440,528 · App. 12/638,480 · Granted May 14, 2013

Method for manufacturing a vertical nonvolatile semiconductor memory device including forming floating gates within the recesses created on the interlayer insulating films

Inventors: Masaru Kito (Kanagawa-ken, JP); Masaru Kidoh (Tokyo, JP); Tomoko Fujiwara (Kanagawa-ken, JP); Yosuke Komori (Kanagawa-ken, JP); Megumi Ishiduki (Kanagawa-ken, JP); Hiroyasu Tanaka (Tokyo, JP); Yoshiaki Fukuzumi (Kanagawa-ken, JP); Ryota Katsumata (Kanagawa-ken, JP); Ryouhei Kirisawa (Kanagawa-ken, JP); Junya Matsunami (Kanagawa-ken, JP); Hideaki Aochi (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,440,528
App. No.
12/638,480
Granted
May 14, 2013
Kind
B2
Abstract

A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

Claims (25)

1. A method for manufacturing a nonvolatile semiconductor memory device comprising:

forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes;

forming a through-hole extending in a stacking direction in the stacked body;

etching a portion of the interlayer insulating films facing the through-hole via the through-hole to remove the portion;

forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed;

forming a floating gate electrode made of conductive material on the first insulating film in the portion in which the interlayer insulating film is removed;

forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and

burying a semiconductor pillar in the through-hole,

wherein wet etching is performed as the etching.

2. A method for manufacturing a nonvolatile semiconductor memory device comprising:

forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes;

forming a through-hole extending in a stacking direction in the stacked body;

etching a portion of the interlayer insulating films facing the through-hole via the through-hole to remove the portion:,

forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed;

forming a floating gate electrode made of conductive material on the first insulating film in the portion in which the interlayer insulating film is removed;

forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and

burying a semiconductor pillar in the through-hole,

wherein

the forming the floating gate electrode includes:

forming a semiconductor layer on inner faces of the through-hole and the portion in which the interlayer insulating film is removed;

removing the semiconductor layer from a bottom face of the through-hole by anisotropic etching; and

removing the semiconductor layer from a side face of the through-hole by isotropic etching.

3. The method according to claim 2 , wherein the forming the semiconductor layer is performed by depositing silicon by low pressure chemical vapor deposition.

4. The method according to claim 2 , wherein the anisotropic etching is performed by reactive ion etching.

5. The method according to claim 2 , wherein the isotropic etching is performed by chemical dry etching.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2009
From: KITO, MASARU; KIDOH, MASARU; FUJIWARA, TOMOKO; KOMORI, YOSUKE; ISHIDUKI, MEGUMI; TANAKA, HIROYASU; FUKUZUMI, YOSHIAKI; KATSUMATA, RYOTA; KIRISAWA, RYOUHEI; MATSUNAMI, JUNYA; AOCHI, HIDEAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023663/0984 →
Priority Claims (1)
JP 2009-012052 · Jan 22, 2009 · national
Continuity (1)
Related Publication 20100181612A1 · Jul 22, 2010