Granted Patent B2

US 9,503,088 · App. 14/655,150 · Granted Nov 22, 2016

Abstract

Claims (27)

1. A method for recovering NBTI/PBTI related parameter degradation in at least one MOSFET device, comprising:

operating the at least one MOSFET device in a standby mode;

exiting the at least one MOSFET device from the standby mode;

holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode; and

operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

2. The method of claim 1 , wherein the at least one MOSFET device comprises at least one n-channel MOSFET device or at least one p-channel MOSFET device.

3. The method of claim 2 , wherein the at least one MOSFET device comprises at least one n-channel MOSFET device and at least one p-channel MOSFET device.

4. The method of one of claim 1 , wherein the operating the at least one MOSFET device in a standby mode comprises continuously keeping the gate voltage of the at least one MOSFET device biased with respect to the drain or source voltage of the at least one MOSFET device.

5. The method of claim 4 , wherein the holding the at least one MOSFET device in an active state comprises reducing the bias of the gate voltage of the at least one MOSFET device with respect to the drain or source voltage of the at least one MOSFET device at least partially for the predetermined time span.

6. The method of claim 1 , wherein the predetermined time span has a duration of 1 ns to 1 ms.

7. The method of claim 1 , wherein the predetermined time span has a duration of 10 ns to 500 ns.

8. The method of claim 1 , wherein the operational mode comprises toggling the at least one MOSFET device according to its intended function.

9. A control device for recovering NBTI/PBTI related parameter degradation in at least one MOSFET device, comprising:

an output configured to be operably connected to the at least one MOSFET device;

a driver module coupled to the output and configured to provide a gate driver signal to the gate of the at least one MOSFET device;

a control module coupled to the driver module and configured to input a gate control signal for the at least one MOSFET device to the driver module;

an input configured to receive an operation activation signal for the at least one MOSFET device; and

a timing module coupled to the input, the control module and the driver module, the timing module configured to receive the operation activation signal, to output a first activation signal to the driver module causing the driver module to hold the at least one MOSFET device in an active state for a predetermined time span after receiving the first activation signal, and to output a second activation signal to the control module causing the control module to generate gate control signals according to an operational mode of the at least one MOSFET device after the predetermined time span has elapsed.

10. The control device of claim 9 , wherein the timing module is configured to output the first activation signal after the gate voltage of the at least one MOSFET device has been continuously kept biased with respect to the drain or source voltage of the at least one MOSFET device.

11. The control device of claim 10 , wherein the first activation signal causes the driver module output the gate driver signal to reduce the bias of the gate voltage of the at least one MOSFET device with respect to the drain or source voltage of the at least one MOSFET device at least partially for the predetermined time span.

12. The control device of claim 9 , wherein the predetermined time span has a duration of 1 ns to 1 ms.

13. The method of claim 9 , wherein the predetermined time span has a duration of 10 ns to 500 ns.

14. An integrated circuit, comprising:

the control device of claim 9 ; and

at least one MOSFET device operably connected to the output of the control device.

15. The integrated circuit of claim 14 , wherein the at least one MOSFET device comprises at least one n-channel MOSFET device or at least one p-channel MOSFET device.

16. The method of claim 15 , wherein the at least one MOSFET device comprises at least one n-channel MOSFET device and at least one p-channel MOSFET device.

Assignments (24)