Method for integrating non-volatile memory cells with static random access memory cells and logic transistors
View Patent ↗A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.
1. A method of making a semiconductor device, the method comprising:
depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate;
depositing a first anti-reflective coating (ARC) layer over the first polysilicon layer;
patterning the first ARC layer and the first polysilicon layer to form a first gate in the NVM region while the first ARC layer and the first polysilicon layer remains in the logic region;
forming a memory cell including the first gate in the NVM region while the first ARC layer and first polysilicon layer remains in the logic region;
removing the first ARC layer and the first layer of polysilicon in the logic region;
implanting source/drain extension regions of the memory cell before depositing a logic gate polysilicon layer in the NVM region and the logic region;
patterning the logic gate polysilicon layer to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region; and
concurrently implanting source/drain regions of the memory cell and the second gate.
2. The method of claim 1 , wherein the first gate in the NVM region is characterized as a select gate, the forming the memory cell comprising:
forming a charge storage layer over the select gate and over the logic region;
depositing a second polysilicon layer over the charge storage layer;
depositing a second ARC layer over the second polysilicon layer;
patterning the second ARC layer and the second polysilicon layer to form a control gate over a portion of a top and sidewall of the select gate while the second ARC layer and the second polysilicon layer is removed from the logic region; and
removing the charge storage layer from areas of the NVM region that do not underlie the control gate and from the logic region.
3. The method of claim 2 , wherein the charge storage layer includes one or more nanocrystals for storing charge.
4. The method of claim 2 , wherein the charge storage layer includes an oxide-nitride-oxide (ONO) stacked layer for storing charge.
5. The method of claim 2 , wherein the memory cell is characterized as a split-gate NVM cell.
6. The method of claim 1 , wherein the substrate further comprises a high-voltage region, the method further comprising:
depositing the logic gate polysilicon layer in the high-voltage region;
patterning the logic gate polysilicon layer to form a third gate in the high-voltage region; and
forming a high voltage transistor including the third gate in the high voltage region.
7. The method of claim 6 , further comprising forming an oxide layer in the high-voltage region while the first ARC layer and first polysilicon layer remains in the logic region.
8. The method of claim 1 , wherein both of the first ARC layer and the second ARC layer includes a nitride material.
9. The method of claim 1 , further comprising forming an SRAM memory cell including the second gate in the logic region.
10. A method of making a semiconductor device, the method comprising:
depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate;
depositing a first anti-reflective coating (ARC) layer over the first polysilicon layer;
selectively etching the first ARC layer and the first polysilicon layer to form a first gate in the NVM region while the first ARC layer and the first polysilicon layer remains in the logic region;
forming a split-gate memory cell including the first gate in the NVM region while the first ARC layer and first polysilicon layer remains in the logic region;
removing the first ARC layer and the first layer of polysilicon in the logic region;
implanting source/drain extensions in the NVM region before depositing a logic gate polysilicon layer in the NVM region and the logic region;
selectively etching the logic gate polysilicon layer to form a second gate in the logic region while removing the logic gate polysilicon layer from the NVM region; and
concurrently forming source/drain regions of the memory cell and the second gate.
11. The method of claim 10 , wherein the first gate in the NVM region is characterized as a select gate, the forming the split-gate memory cell comprising:
forming a charge storage layer over the select gate and over the logic region;
depositing a second polysilicon layer over the charge storage layer;
depositing a second ARC layer over the second polysilicon layer;
selectively etching the second ARC layer and the second polysilicon layer to form a control gate over a portion of a top and sidewall of the select gate while the second ARC layer and the second polysilicon layer is removed from the logic region; and
selectively etching the charge storage layer from areas of the NVM region that do not underlie the control gate and from the logic region.
12. The method of claim 11 , wherein the charge storage layer includes one or more nanocrystals for storing charge or an oxide-nitride-oxide (ONO) stacked layer for storing charge.
13. The method of claim 11 , wherein implanting source/drain extensions in the NVM region further comprises implanting source/drain extensions in the NVM region before selectively etching the second ARC layer.
14. The method of claim 10 , wherein forming source/drain regions includes deep implanting of the source/drain regions.
15. The method of claim 10 , wherein the first ARC layer includes a nitride material.
16. The method of claim 10 , further comprising forming an SRAM memory cell including the second gate in the logic region.
17. The method of claim 10 , wherein selectively etching the logic gate polysilicon layer further comprises forming a third gate in the logic region, the third gate having a different dielectric thickness than the second gate.