IP Library › Granted Patent US 9,564,493
Granted Patent B2
US 9,564,493 · App. 14/656,948 · Granted Feb 7, 2017

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Inventors: Jean-Pierre Colinge (Hsin-Chu, TW); Carlos H. Diaz (Hsin-Chu, TW); Yee-Chia Yeo (Singapore, SG)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/267H01L21/02521H01L21/02573H01L21/02667H01L21/477H01L21/823412H01L21/823487H01L27/088H01L29/04H01L29/1033H01L29/66969H01L29/7827
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,564,493
App. No.
14/656,948
Granted
Feb 7, 2017
Kind
B2
Abstract

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Claims (55)

1. A structure comprising:

a substrate having an upper surface;

a first source/drain contact region;

a channel structure connected to and over the first source/drain contact region, the channel structure being over the upper surface of the substrate, the channel structure having a sidewall extending above the first source/drain contact region, the channel structure comprising a bismuth-containing semiconductor material;

a gate dielectric along the sidewall of the channel structure;

a gate electrode along the gate dielectric; and

a second source/drain contact region connected to and over the channel structure.

2. The structure of claim 1 , wherein the bismuth-containing semiconductor material is doped bismuth (Bi).

3. The structure of claim 1 , wherein the channel structure has a cross section area in a plane parallel to the upper surface of the substrate, the cross section area having a largest dimension of 53 nm or less.

4. The structure of claim 1 , wherein the bismuth-containing semiconductor material is doped with a p-type dopant.

5. The structure of claim 1 , wherein the bismuth-containing semiconductor material is doped with an n-type dopant.

6. The structure of claim 1 , wherein the bismuth-containing semiconductor material is monocrystalline.

7. The structure of claim 1 , wherein the bismuth-containing semiconductor material does not have a p-n junction.

8. The structure of claim 1 , wherein the first source/drain contact region is over the upper surface of the substrate, the first source/drain contact region comprising a substantially pure metal, a semiconductor-metal compound, or a combination thereof.

9. The structure of claim 1 , wherein the substrate is a semiconductor substrate, the first source/drain contact region comprising a doped semiconductor region in the semiconductor substrate.

10. The structure of claim 1 , wherein the substrate comprises:

a semiconductor substrate;

devices on the semiconductor substrate; and

interconnect structures on the semiconductor substrate, the interconnect structures comprising an upper dielectric layer, the upper surface of the substrate—in contact with a surface of the upper dielectric layer.

11. A structure comprising:

a substrate comprising a horizontal surface, the horizontal surface being an upper surface of the substrate;

a first vertical channel transistor over the horizontal surface of the substrate, the first vertical channel transistor comprising:

a first source/drain contact region,

a first bismuth-containing channel structure connected to and over the first source/drain contact region, the first bismuth-containing channel structure being a semiconductor and comprising an n-type dopant, the first bismuth-containing channel structure extending perpendicular to the horizontal surface,

a first gate dielectric around the first bismuth-containing channel structure,

a first gate electrode around the first gate dielectric, the first gate dielectric being disposed between the first bismuth-containing channel structure and the first gate electrode, and

a second source/drain contact region connected to and over the first bismuth-containing channel structure; and

a second vertical channel transistor over the horizontal surface of the substrate, the second vertical channel transistor comprising:

a third source/drain contact region,

a second bismuth-containing channel structure connected to and over the third source/drain contact region, the second bismuth-containing channel structure being a semiconductor and comprising a p-type dopant, the second bismuth-containing channel structure extending perpendicular to the horizontal surface,

a second gate dielectric around the second bismuth-containing channel structure,

a second gate electrode around the second gate dielectric, the second gate dielectric being disposed between the second bismuth-containing channel structure and the second gate electrode, and

a fourth source/drain contact region connected to and over the second bismuth-containing channel structure.

12. The structure of claim 11 , wherein a cross section of the first bismuth-containing channel structure in a plane parallel to the horizontal surface has a largest dimension 53 nm or less, and a cross section of the second bismuth-containing channel structure in a plane parallel to the horizontal surface has a largest dimension 53 nm or less.

13. The structure of claim 11 , wherein the first bismuth-containing channel structure and the second bismuth-containing channel structure each comprise a monocrystalline bismuth-containing material.

14. The structure of claim 11 , wherein the first source/drain contact region and the third source/drain contact region are over the horizontal surface of the substrate, the first source/drain contact region and the third source/drain contact region each comprising a substantially pure metal, a semiconductor-metal compound, or a combination thereof.

15. The structure of claim 11 , wherein the substrate is a semiconductor substrate, the first source/drain contact region comprising an n-doped region in the semiconductor substrate, and the third source/drain contact region comprises a p-doped region in the semiconductor substrate.

16. The structure of claim 11 , wherein the substrate comprises:

a semiconductor substrate;

devices on the semiconductor substrate; and

interconnect structures on the semiconductor substrate, the interconnect structures comprising an upper dielectric layer, the horizontal surface of the substrate—in contact with a surface of the upper dielectric layer.

17. A structure comprising:

a substrate having an upper surface;

a first source/drain contact region;

a first channel structure connected to and over the first source/drain contact region, the first channel structure being over the upper surface of the substrate, the first channel structure having a first sidewall extending above the first source/drain contact region, the first channel structure comprising a first bismuth-containing semiconductor material;

a first gate dielectric along the first sidewall of the first channel structure;

a first gate electrode along the first gate dielectric;

a second source/drain contact region connected to and over the first channel structure;

a third source/drain contact region over the second source/drain contact region;

a second channel structure connected to and over the third source/drain contact region, the second channel structure having a second sidewall extending above the third source/drain contact region, the second channel structure comprising a second bismuth-containing semiconductor material;

a second gate dielectric along the second sidewall of the second channel structure; and

a second gate electrode along the second gate dielectric.

18. The structure of claim 17 , further comprising an interconnect structure interposed between the second source/drain contact region and the third source/drain contact region.

19. The structure of claim 18 , wherein the first gate electrode is electrically coupled to the third source/drain contact region.

20. The structure of claim 17 , wherein the first and second bismuth-containing semiconductor materials comprise doped bismuth (Bi).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2015
From: COLINGE, JEAN-PIERRE; DIAZ, CARLOS H.; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 035403/0949 →
Continuity (1)
Related Publication 20160268382A1 · Sep 15, 2016