Semiconductor memory device and semiconductor device and electronic device having the same
View Patent ↗A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.
1. A semiconductor memory device comprising:
a first memory cell and a second memory cell adjacent to the first memory cell, each of the first memory cell and the second memory cell comprising:
a first transistor, a gate of the first transistor being electrically connected to a first wiring, one of a source and a drain of the first transistor being electrically connected to a fourth wiring, and the other of the source and the drain of the first transistor being electrically connected to a node;
a second transistor, a gate of the second transistor being electrically connected to the node, one of a source and a drain of the second transistor being electrically connected to a third wiring, and the other of the source and the drain of the second transistor being electrically connected to a fifth wiring; and
a capacitor, one electrode of the capacitor being electrically connected to the node, and the other electrode of the capacitor being electrically connected to a second wiring,
wherein a channel formation region of the first transistor comprises an oxide semiconductor layer,
wherein each of a channel length and a channel width of the first transistor is shorter than 100 nm,
wherein a maximum potential of the first wiring is lower than or equal to 2 V, and
wherein electrostatic capacitance of the capacitor is greater than or equal to 5 aF and less than or equal to 200 aF.
2. The semiconductor memory device according to claim 1 , wherein the first transistor comprises a pair of gates with the oxide semiconductor layer provided therebetween.
3. The semiconductor memory device according to claim 1 , wherein the second transistor is a p-channel transistor.
4. The semiconductor memory device according to claim 1 , wherein the third wiring is shared by the first memory cell and the second memory cell.
5. A semiconductor memory device comprising:
a first memory cell and a second memory cell adjacent to the first memory cell, each of the first memory cell and the second memory cell comprising:
a first transistor, a gate of the first transistor being electrically connected to a first wiring, one of a source and a drain of the first transistor being electrically connected to a fourth wiring, and the other of the source and the drain of the first transistor being electrically connected to a node;
a second transistor, a gate of the second transistor being electrically connected to the node, and one of a source and a drain of the second transistor being electrically connected to a third wiring; and
a third transistor, a gate of the third transistor being electrically connected to a second wiring, and one of a source and a drain of the third transistor being electrically connected to the other of the source and the drain of the second transistor,
wherein a channel formation region of the first transistor comprises an oxide semiconductor layer,
wherein each of a channel length and a channel width of the first transistor is shorter than 100 nm, and
wherein a maximum potential of the first wiring is lower than or equal to 2 V.
6. The semiconductor memory device according to claim 5 , wherein the first transistor comprises a pair of gates with the oxide semiconductor layer provided therebetween.
7. The semiconductor memory device according to claim 5 , wherein the other of the source and the drain of the third transistor is electrically connected to the fourth wiring.
8. The semiconductor memory device according to claim 5 , wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring.
9. The semiconductor memory device according to claim 5 , wherein each of the second transistor and the third transistor is a p-channel transistor.
10. The semiconductor memory device according to claim 5 , wherein the third wiring is shared by the first memory cell and the second memory cell.
11. A semiconductor memory device comprising:
a first memory cell and a second memory cell adjacent to the first memory cell, each of the first memory cell and the second memory cell comprising:
a first transistor, a gate of the first transistor being electrically connected to a first wiring, one of a source and a drain of the first transistor being electrically connected to a fourth wiring, and the other of the source and the drain of the first transistor being electrically connected to a node;
a second transistor, a gate of the second transistor being electrically connected to the node, and one of a source and a drain of the second transistor being electrically connected to a third wiring;
a third transistor, a gate of the third transistor being electrically connected to a second wiring, and one of a source and a drain of the third transistor being electrically connected to the other of the source and the drain of the second transistor; and
a capacitor, one electrode of the capacitor being electrically connected to the node, and the other electrode of the capacitor being electrically connected to a sixth wiring,
wherein a channel formation region of the first transistor comprises an oxide semiconductor layer,
wherein each of a channel length and a channel width of the first transistor is shorter than 100 nm,
wherein a maximum potential of the first wiring is lower than or equal to 2 V, and
wherein electrostatic capacitance of the capacitor is greater than or equal to 5 aF and less than or equal to 200 aF.
12. The semiconductor memory device according to claim 11 , wherein the first transistor comprises a pair of gates with the oxide semiconductor layer provided therebetween.
13. The semiconductor memory device according to claim 11 , wherein the other of the source and the drain of the third transistor is electrically connected to the fourth wiring.
14. The semiconductor memory device according to claim 11 , wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring.
15. The semiconductor memory device according to claim 11 , wherein each of the second transistor and the third transistor is a p-channel transistor.
16. The semiconductor memory device according to claim 11 , wherein the third wiring is shared by the first memory cell and the second memory cell.