IP Library Granted Patent US 10,468,347
Granted Patent B2
US 10,468,347 · App. 14/660,759 · Granted Nov 5, 2019

Semiconductor device including fully-silicided liner extending over a contact plug and insulating layer

Inventor: Tomohiro Kadoya (Tokyo, JP)
Assignee: Micron Technology, Inc.
H01L23/528H01L27/10811H01L27/10817H01L27/10823H01L27/10855H01L27/10876H01L27/10885H01L27/10891H01L27/10894H01L2924/0002
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Quick Facts
Patent No.
US 10,468,347
App. No.
14/660,759
Granted
Nov 5, 2019
Kind
B2
Abstract

Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.

Claims (41)

1. A device comprising:

a substrate;

a contact plug disposed on the substrate and being a bit contact;

an interlayer dielectric over the substrate to define the contact plug;

wherein the contact plug comprises:

a bottom portion facing to the substrate;

a side portion being adjacent to the interlayer dielectric;

a metal silicide comprising a cup shape that extends along the bottom and the side portions of the contact plug, the metal silicide along the bottom of the contact plug being against a diffusion region of the substrate;

a metal nitride liner covering an inner surface of the cup shape of the metal silicide; and

a metal plug disposed in an inner portion of the metal nitride liner;

a bit line which includes titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, the titanium silicide of the bit line being over and in contact with each of the metal silicide, the metal nitride liner, and the metal plug of the contact plug; and

a conductive material disposed over the titanium silicide.

2. The device according to claim 1 , further comprising silicon layer between the metal silicide and the interlayer dielectric.

3. The device according to claim 1 , further comprising:

a groove being located in the substrate; and

a word line disposed in a lower portion of the groove, wherein the interlayer dielectric is disposed in an upper portion of the groove and protrudes from an upper surface of the substrate.

4. The device according to claim 3 , further comprising:

an isolation region in the substrate;

an active region surrounded by the isolation region in the substrate; and

an additional groove prolonging in parallel with the groove, the groove and the additional groove each intersecting the active region and each extending continuously from the active region to the isolation region.

5. The device according to claim 4 , wherein the word line extends continuously from the active region to the isolation region.

6. The device according to claim 5 , further comprising:

a field insulator covering the isolation region;

a cell gate insulator covering an inner surface of the groove and extending continuously from the active region to the isolation region, the word, line covering the cell gate insulator.

7. A device comprising:

a substrate;

a bit line over the substrate and comprising titanium silicide; wherein the titanium silicide of the bit line comprises a first portion being located on a first conductive material that is in contact with the substrate, and comprises a second portion being located on an interlayer dielectric that is adjacent to the first conductive material; and

wherein the first conductive material is a bit contact and comprises:

a bottom portion facing the substrate;

a side portion being adjacent to the interlayer dielectric;

an additional metal silicide comprising a cup shape that surrounds the bottom and the side portions;

a metal nitride material covering an inner surface of the cup shape; and

a metal plug disposed in an inner portion of the metal nitride material, the titanium silicide of the bit line contacting each of the additional metal silicide, the metal nitride material, and the metal plug of the first conductive material.

8. A device comprising:

a substrate;

a first metal silicide comprising a cup shape including a bottom portion facing to the substrate;

an interlayer dielectric surrounding an outer surface of the first metal silicide;

a metal material disposed in an inner portion of the cup shape of the first metal silicide and being spaced from the first metal silicide by a metal nitride material, the first metal silicide, the metal nitride material and the metal material together being comprised by a bit contact; and

a bit line containing a second metal silicide extending continuously on and directly contacting each of the respective upper portions of the interlayer dielectric, the first metal silicide, the metal nitride material and the metal material.

9. The device according to claim 8 , wherein the first and second metal silicide each comprises one of an element in a group that consist of titanium, cobalt, nickel, and platinum.

10. The device according to claim 8 , further comprising silicon layer between the first metal silicide and the interlayer dielectric.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2015
From: KADOYA, TOMOHIRO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 035185/0964 →