IP Library Granted Patent US 9,569,264
Granted Patent B2
US 9,569,264 · App. 14/660,905 · Granted Feb 14, 2017

Multi-core system for processing data packets

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Quick Facts
Patent No.
US 9,569,264
App. No.
14/660,905
Granted
Feb 14, 2017
Kind
B2
Abstract

A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

Claims (61)

1. A multi-core system for processing a plurality of threads, the multi-core system comprising:

a memory for storing the plurality of threads, a plurality of data packets, and a plurality of buffer descriptor (BD) rings corresponding to the plurality of threads, wherein each BD ring includes a plurality of BDs, and wherein a BD corresponds to a data packet;

a host processor coupled to the memory and having a plurality of cores,

wherein the host processor is configured for processing the plurality of threads, wherein each of the plurality of cores execute at least one thread of the plurality of the threads,

generating a set of context switch events based on execution states of the plurality of threads, wherein a context switch event is a schedule-in event when a thread is scheduled-in to one of the cores and a schedule-out event when the thread is scheduled-out from the one of the cores,

identifying the set of context switch events,

identifying a set of threads of the plurality of threads based on the set of context switch events,

identifying a set of BD rings of the plurality of BD rings corresponding to the set of threads,

generating a notification command indicative of the set of BD rings and the set of context switch events, and

transmitting the notification command; and

a co-processor, connected to memory and to the host processor for receiving the notification command, polling the set of BD rings based on the notification command, and processing a set of data packets corresponding to the set of BD rings,

wherein the co-processor stores a list of active BD ring IDs and polls the set of BD rings by performing the steps of:

identifying the set of BD rings as a set of active BD rings when the notification command includes the schedule-in event;

modifying the list of active BD ring IDs based on the notification command;

identifying the set of BD rings as a set of inactive BD rings when the notification command includes the schedule-out event;

modifying the list of active BD ring IDs by eliminating the set of inactive BD rings; and

polling the set of active BD rings on the list of active BD ring IDs.

2. The multi-core system of claim 1 , wherein each BD ring has a BD ring identification (ID) and each thread has a thread ID.

3. The multi-core system of claim 2 , wherein the host processor stores a mapping table that includes a mapping between a plurality of BD ring IDs and a corresponding plurality of thread IDs.

4. The multi-core system of claim 1 , wherein the notification command includes at least one BD ring ID and the context switch event.

5. The multi-core system of claim 1 , wherein the co-processor comprises at least one of an Ethernet controller, a cryptographic co-processor, a pattern-matching co-processor, and a compression co-processor.

6. A multi-core system for processing a plurality of threads, the multi-core system comprising:

a memory for storing the plurality of threads, a plurality of data packets, and a plurality of buffer descriptor (BD) rings corresponding to the plurality of threads, wherein each BD ring includes a plurality of BDs, and a BD corresponds to a data packet;

a host processor, having a plurality of cores, that communicates with the memory and is configured for:

processing the plurality of threads, wherein each of the plurality of cores execute at least one thread of the plurality of threads,

generating a set of context switch events based on execution states of the plurality of threads on the corresponding plurality of cores,

generating a context switch event notification command indicative of the set of context switch events, wherein a context switch event is a schedule-in event when a thread is scheduled-in to one of the cores and a schedule-out event when the thread is scheduled-out from the one of the cores, and

transmitting the context switch event notification command by way of a notification bus; and

a co-processor connected to the host processor and the memory, that stores a list of active BD ring IDs, wherein the co-processor:

receives the context switch event notification command,

identifies the set of context switch events based on the context switch event notification command,

identifies a set of threads of the plurality of threads based on the set of context switch events,

identifies a set of BD rings corresponding to the set of threads,

polls the set of BD rings by performing the steps of:

identifying the set of BD rings as a set of active BD rings when the context switch event notification command includes the schedule-in event;

modifying the list of active BD ring IDs based on the context switch event command;

identifying the set of BD rings as a set of inactive BD rings when the context switch event command includes the schedule-out event; and

modifying the list of active BD ring IDs by eliminating a set of BD ring IDs associated with the set of inactive BD rings;

polling the set of active BD rings based on the list of active BD ring IDs, and

processes a set of data packets of the plurality of data packets corresponding to the set of active BD rings.

7. The multi-core system of claim 6 , wherein each BD ring has a corresponding BD ring identification (ID) and each thread has a corresponding thread ID.

8. The multi-core system of claim 7 , wherein the co-processor stores a mapping table that includes a mapping between a plurality of BD ring IDs and a corresponding plurality of thread IDs.

9. The multi-core system of claim 6 , wherein the context switch event notification command includes at least one thread ID and the context switch event.

10. The multi-core system of claim 6 , wherein the co-processor comprises at least one of an Ethernet controller, a cryptographic co-processor, a pattern-matching co-processor, and a compression co-processor.

11. A method of processing a plurality of threads, comprising:

storing the plurality of threads, a plurality of data packets, and a plurality of buffer descriptor (BD) rings corresponding to the plurality of threads in a memory, wherein each BD ring includes a plurality of BDs, and wherein a BD corresponds to a data packet;

processing the plurality of threads with a multi-core processor coupled to the memory, wherein threads are executed in parallel by different cores of the multi-core processor;

generating a set of context switch events based on execution states of the plurality of threads, wherein a context switch event is a schedule-in event when a thread is scheduled-in to one of the cores and a schedule-out event when the thread is scheduled-out from the one of the cores;

identifying a set of threads of the plurality of threads based on the set of context switch events;

identifying a set of BD rings of the plurality of BD rings that correspond to the set of threads;

generating a notification command indicative of the set of BD rings;

transmitting the notification command to a co-processor;

receiving the notification command at the co-processor;

polling the set of BD rings based on the notification command;

identifying the set of BD rings as a set of active BD rings when the notification command includes the schedule-in event;

identifying the set of BD rings as a set of inactive BD rings when the notification command includes the schedule-out event;

modifying a list of active BD ring IDs by eliminating the set of inactive BD rings; and

processing a set of data packets of the plurality of data packets associated with the set of BD rings identified in the list of active BD ring IDs, by the co-processor.

12. The method of claim 11 , wherein each BD ring has a corresponding BD ring identification (ID), and each thread has a corresponding thread ID.

13. The method of claim 12 , wherein the notification command includes the BD ring ID and the context switch event.

14. The method of claim 12 , wherein the notification command includes the thread ID and the context switch event.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0359 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2015
From: GARG, VAKUL; BHUSHAN, BHARAT; GUPTA, RUCHIKA
To: FREESCALE SEMICONDUCTOR, INC
Reel/Frame 035186/0461 →