Low power oscillator with charge subtraction scheme
An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 μm CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (−10° C. to 90° C.) and 1%/V line sensitivity.
1. A low power oscillator, comprising:
an integrating capacitor;
a current source configured to charge the integrating capacitor;
a subtraction circuit electrically coupled to the integrating capacitor and operable to subtract a fixed amount of charge from the integrating capacitor in response to a trigger signal, wherein the current source continues to charge the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor; and
a first comparator configured to receive voltage across the integrating capacitor and compare the capacitor voltage to a first reference voltage, wherein the first comparator provides a trigger signal to the subtraction circuit when the integrating capacitor voltage exceeds the first reference voltage.
2. The low power oscillator of claim 1 further comprises:
a control circuit counts occurrences of the trigger signal generated by the first comparator and generates an activation signal when the number of occurrences equals a predefined number of cycles; and
a second comparator configured to receive voltage across the integrating capacitor and, in response to the activation signal, compares the capacitor voltage to a second reference voltage and outputs a pulse when the capacitor voltage exceeds the second reference voltage.
3. The low power oscillator of claim 2 wherein the output from the second comparator forms a periodic oscillating signal having a frequency based on the predefined number of cycles.
4. The low power oscillator of claim 2 wherein the control circuit deactivates the second comparator after the pulse is output by the second comparator.
5. The low power oscillator of claim 1 wherein the subtraction circuit includes a charging capacitor that selectively couples to the integrating capacitor, wherein the charging capacitor is electrically coupled via an amplifier to the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor but is otherwise electrically isolated from the integrating capacitor.
6. The low power oscillator of claim 1 wherein the subtraction circuit includes
a charging capacitor;
a voltage source electrically coupled via a charging amplifier to charge the charging capacitor and operable to charge the charging capacitor; and
a subtraction amplifier electrically coupled between the charging capacitor and integrating capacitor and operable to discharge voltage from the charging capacitor to the integrating capacitor.
7. A low power oscillator, comprising:
an integrating capacitor;
a current source configured to charge the integrating capacitor;
a subtraction circuit electrically coupled to the integrating capacitor and operable to subtract a fixed amount of charge from the integrating capacitor in response to a trigger signal;
a first comparator configured to receive voltage across the integrating capacitor and compare the capacitor voltage to a first reference voltage, wherein the first comparator provides a trigger signal to the subtraction circuit when the integrating capacitor voltage exceeds the first reference voltage;
a control circuit counts occurrences of the trigger signal generated by the first comparator and generates an activation signal when the number of occurrences equals a predefined number of cycles; and
a second comparator configured to receive voltage across the integrating capacitor and, in response to the activation signal, compares the capacitor voltage to a second reference voltage and outputs a pulse when the capacitor voltage exceeds the second reference voltage.
8. The low power oscillator of claim 7 wherein the output from the second comparator forms a periodic oscillating signal having a frequency based on the predefined number of cycles.
9. The low power oscillator of claim 8 wherein the current source continues to charge the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor.
10. The low power oscillator of claim 9 wherein the control circuit deactivates the second comparator after the pulse is output by the second comparator.
11. The low power oscillator of claim 10 wherein the subtraction circuit includes a charging capacitor that selectively couples to the integrating capacitor, wherein the charging capacitor is electrically coupled via an amplifier to the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor but is otherwise electrically isolated from the integrating capacitor.
12. The low power oscillator of claim 11 wherein the subtraction circuit includes
a charging capacitor;
a voltage source electrically coupled via a charging amplifier to charge the charging capacitor and operable to charge the charging capacitor; and
a subtraction amplifier electrically coupled between the charging capacitor and integrating capacitor and operable to discharge voltage from the charging capacitor to the integrating capacitor.
13. A method for generating a periodic oscillating signal, comprising:
(a) charging an integrating capacitor using a current source;
(b) comparing voltage across the capacitor to a first reference voltage using a first comparator circuit;
(c) subtracting a fixed amount of charge from the integrating capacitor while continuing to charge the integrating capacitor, the subtraction occurring in response to the voltage across the integrating capacitor exceeding the first reference voltage;
(d) incrementing a counter;
repeating steps (a)-(d) for a predefined number of cycles;
activating a second comparator circuit, the activation occurring in response to value of the counter value equaling the predefined number of cycles;
comparing voltage across the integrating capacitor to a second reference voltage using the second comparator circuit; and
generating a pulse by the second comparator circuit, the generation occurring in response to the voltage across the integrating capacitor exceeding the second reference voltage.
14. The method of claim 13 further comprises deactivating the second comparator circuit after the pulse is output by the second comparator circuit.
15. The method of claim 13 further comprises initializing the counter to zero and continuing with execution of step (a) after the step of generating a pulse.
16. The method of claim 13 further comprises subtracting a fixed amount of charge using a subtraction circuit, where the subtraction circuit includes a charging capacitor that selectively couples to the integrating capacitor and the charging capacitor is electrically coupled via an amplifier to the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor but is otherwise electrically isolated from the integrating capacitor.
17. A low power oscillator, comprising:
an integrating capacitor;
a current source configured to charge the integrating capacitor;
a subtraction circuit electrically coupled to the integrating capacitor and operable to subtract a fixed amount of charge from the integrating capacitor in response to a trigger signal; and
a first comparator configured to receive voltage across the integrating capacitor and compare the capacitor voltage to a first reference voltage, wherein the first comparator provides a trigger signal to the subtraction circuit when the integrating capacitor voltage exceeds the first reference voltage, wherein the subtraction circuit includes a charging capacitor that selectively couples to the integrating capacitor, wherein the charging capacitor is electrically coupled via an amplifier to the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor but is otherwise electrically isolated from the integrating capacitor.