Granted Patent B2

US 10,042,789 · App. 14/662,280 · Granted Aug 7, 2018

Abstract

Claims (45)

1. An apparatus, comprising:

a memory array; and

a controller configured to:

detect an interruption during a programming operation by detecting signal toggle using a number of trims set in the controller; and

modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.

2. The apparatus of claim 1 , wherein the controller is configured to detect the interruption during the programming operation by detecting a voltage drop below a threshold level.

3. The apparatus of claim 1 , wherein the controller is configured to modify the programming operation by setting data latches on all active pages to accept a programming signal.

4. The apparatus of claim 3 , wherein the controller is configured to modify the programming operation by providing the programming signal to program all memory cells of the active pages.

5. The apparatus of claim 3 , wherein the controller is configured to detect and flag each of the pages programmed to the uncorrectable state as being programmed during the interruption in the programming operation.

6. The apparatus of claim 1 , wherein the controller is configured to move data from the block having the pages programmed to the uncorrectable state to a new block.

7. The apparatus of claim 1 , wherein the controller is configured to detect pages programmed to the uncorrectable state as being corrupt.

8. A method for managing a programming interruption, comprising:

detecting an interruption in a programming operation by detecting signal toggle using a number of trims set in the controller; and

modifying the programming operation in response to detecting the interruption in the programming operations by providing a modified programming signal that programs active pages of the programming operation to an uncorrectable state.

9. The method of claim 8 , wherein providing the modified programming signal programs memory cells that have completed a lower page programming process to the uncorrectable state.

10. The method of claim 8 , wherein the method includes detecting the active pages programmed to the uncorrectable state as corrupted and moving data from pages on block containing the active pages programmed to the uncorrectable state to a new block.

11. The method of claim 8 , wherein the method includes selecting active pages of the programming operation by setting data latches of the active pages to accept the modified programming signal.

12. The method of claim 8 , wherein detecting the interruption in the programming operation includes detecting a signal toggle that indicates the programming operation cannot be completed.

13. The method of claim 8 , wherein detecting the interruption in the programming operation includes detecting a power loss.

14. A method for managing a programming interruption, comprising:

detecting an interruption in a programming operation by detecting a signal toggle using a number of trims set in the controller;

setting data latches for active pages of the programming operations to accept a programming signal; and

applying a programming signal to memory cells of the active pages, wherein the programming signal programs the memory cells of the active pages to an uncorrectable state.

15. The method of claim 14 , wherein applying the programming signal includes applying the programming signal that corresponds to the highest voltage threshold state for the memory cells of the active pages.

16. The method of claim 14 , wherein applying the programming signal causes a programming pattern of the programming operation to be lost.

17. The method of claim 14 , wherein the method includes intentionally corrupting the active pages by applying the programming signal.

18. The method of claim 14 , wherein detecting the interruption in the programming operation includes detecting a signal toggle that indicates the programming operation will be prematurely terminated.

19. The method of claim 14 , wherein detecting the interruption in the programming operation includes detecting a power loss.

20. An apparatus, comprising:

a memory array; and

a controller configured to:

detect an interruption in a programming operation by detecting a signal toggle using a number of trims set in the controller;

apply a programming signal to memory cells of the memory array that programs the memory cells to an uncorrectable state.

21. The apparatus of claim 20 , wherein the controller is configured to set data latches for active pages of the programming operations to accept the programming signal.

22. The apparatus of claim 20 , wherein the controller is configured to detect the uncorrectable state of the memory cells by detecting a number of errors that is greater than which can be corrected by an error correction (ECC) operation.

23. The apparatus of claim 20 , wherein the controller is configured to modify the programming operation by providing the programming signal to program the lower page of the memory cells.

24. The apparatus of claim 20 , wherein the controller is configured to skip applying the programming signal to a number of pages that include an upper page flag indicating that an upper page programming operation has been performed.

25. A method for managing a programming interruption, comprising:

detecting an interruption in a programming operation via a signal toggle; and

intentionally corrupting a number of pages of memory cells to an uncorrectable state in response to detecting the interruption.

26. The method of claim 25 , wherein detecting the interruption in the programming operation includes detecting that a signal drops below a threshold voltage.

27. The method of claim 25 , wherein intentionally corrupting the number of pages of memory cells includes applying a modified programming signal to the number of pages of memory cells that programs the number of pages of memory cells to an uncorrectable data state.

28. The method of claim 25 , including intentionally corrupting the number of pages of memory cells that were undergoing a lower page programming operation when the interruption occurred.

29. The method of claim 25 , including intentionally corrupting the number of pages of memory cells that were undergoing an upper page programming operation when the interruption occurred.

30. The method of claim 25 , including moving data from a block containing the corrupt number of pages of memory cells using a wear leveling operation.

Assignments (8)