INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.
1 . An Integrated Circuit (IC) chip including a plurality of Field Effect Transistor (FET) connected together into one or more circuits, said IC comprising:
a plurality of silicon islands in a surface silicon layer of a Silicon On Insulator (SOI) wafer;
a FET having a metal gate on at least one said silicon island, each said FET being a metal gate FET;
one or more FET having a polysilicon gate on one or more other said silicon island, each said FET being a silicon gate FET; and
wiring connecting FETs together into one or more IC circuits.
2 . An IC as in claim 1 , wherein silicon gate FETs comprise a silicon channel, a gate oxide layer on said silicon channel, and a polysilicon gate above said gate oxide layer.
3 . An IC as in claim 2 , wherein shallow trench oxide (STI) separates said silicon islands, said IC further comprising at least one fuse comprising:
a polysilicon segment on oxide, an upper surface of said oxide being coplanar with an upper surface of an adjacent island;
a silicide layer on said polysilicon segment; and
contacts at opposite ends of said silicide layer.
4 . An IC as in claim 2 , wherein said high-k dielectric is selected from Zirconium Oxide (ZrO 5 ) and hafnium dioxide (HfO 2 ), said metal gate includes a work function metal selected from Aluminum (Al), Titanium Nitride (TiNi), and Titanium Aluminum (TiAl) and said silicon gate FETs and said metal gate FETs comprise further comprise Silicon Germanium (SiGe) source/drains.
5 . An IC as in claim 4 , further comprising a Nickel silicide (NiSi) layer on each SiGe source/drain and a tungsten pad on each said NiSi layer, said wiring connecting to the tungsten pads.
6 . An IC as in claim 5 , wherein said metal gate FETs comprise a silicon channel, a hi-k dielectric layer on said silicon channel, and a metal gate on said a hi-K dielectric layer.
7 . An IC as in claim 6 , wherein said gate oxide layer in one or more of said silicon gate FETs is thicker than other silicon gate FETs in said IC and at least one said silicon gate FET is a P-type FET (PFET).
8 . An IC as in claim 1 , wherein
silicon gate FETs comprise a silicon channel, a gate oxide layer on said silicon channel, and a polysilicon gate above said gate oxide layer; and
said metal gate FETs comprise a silicon channel, a hi-k dielectric layer on said silicon channel, and a metal gate on said a hi-K dielectric layer.
9 . An IC as in claim 8 , wherein said high-k dielectric is selected from Zirconium Oxide (ZrO 5 ) and hafnium dioxide (HfO 2 ), said metal gate includes a work function metal selected from Aluminum (Al), Titanium Nitride (TiNi), and Titanium Aluminum (TiAl) and said silicon gate FETs and said metal gate FETs comprise further comprise Silicon Germanium (SiGe) source/drains.
10 . An IC as in claim 9 , wherein said gate oxide layer in one or more of said silicon gate FETs is thicker than other silicon gate FETs in said IC and at least one said silicon gate FET is a P-type FET (PFET).
11 . An IC as in claim 10 , further comprising a Nickel silicide (NiSi) layer on each SiGe source/drain and a tungsten pad on each said NiSi layer, said wiring connecting to the tungsten pads.
12 . An IC as in claim 11 , wherein shallow trench oxide (STI) separates said silicon islands, said IC further comprising at least one fuse comprising:
a polysilicon segment on oxide, an upper surface of said oxide being coplanar with an upper surface of an adjacent island;
a silicide layer on said polysilicon segment; and
contacts at opposite ends of said silicide layer.
13 . An Integrated Circuit (IC) chip including a plurality of Field Effect Transistor (FET) connected together into one or more circuits, said IC comprising:
a plurality of silicon islands in a surface silicon layer of a Silicon On Insulator (SOI) wafer, said silicon islands being defined and separated from each other by shallow trench isolation (STI) through a surface silicon layer to a buried oxide layer;
a FET having a metal gate on at least one said silicon island, each said FET being a metal gate FET comprising a silicon channel, a hi-k dielectric layer on said silicon channel, and a metal gate on said a hi-K dielectric layer;
one or more FET having a polysilicon gate on one or more other said silicon island, each said FET being a silicon gate FET comprising a silicon channel, a gate oxide layer on said silicon channel, and a polysilicon gate above said gate oxide layer;
a gate silicide layer on each polysilicon gate;
Silicon Germanium (SiGe) source/drains at each FET;
a source/drain silicide layer on each SiGe source/drain; and
wiring to the silicide layers and metal gates connecting FETs together into one or more IC circuits.
14 . A IC as in claim 13 wherein at least one said silicon gate FET being a P-type FET (PFET),
wherein one or more of said silicon gate FETs further comprise an electrolytic layer on said gate oxide layer, said polysilicon gate being on said electrolytic layer, at least one polysilicon gate being on said gate oxide layer, and
wherein said high-k dielectric is selected from Zirconium Oxide (ZrO 5 ) and hafnium dioxide (HfO 2 ), said metal gate includes a work function metal selected from Aluminum (Al), Titanium Nitride (TiNi), and Titanium Aluminum (TiAl), said gate silicide layer is cobalt silicide (CoSi), said source/drain silicide layer is Nickel silicide (NiSi) source/drain layer on each SiGe source/drain, and said further comprises a tungsten pad on each said NiSi source/drain layer, said wiring connecting to the tungsten pads.
15 . A IC as in claim 13 , further including at least one fuse in one circuit of said one or more IC circuits, said at least one fuse comprising:
a polysilicon segment on oxide, an upper surface of said oxide being coplanar with an upper surface of an adjacent island;
a silicide layer on said polysilicon segment; and
contacts at opposite ends of said silicide layer, said wiring connecting said at least one fuse into one circuit, the presence of said fuse placing said one circuit in a first state, and opening said fuse placing said one circuit in a second state.
16 . An IC as in claim 13 , wherein said gate oxide layer in one or more of said silicon gate FETs is thicker than other silicon gate FETs in said IC and at least one said silicon gate FET is a P-type FET (PFET).
17 . An Integrated Circuit (IC) chip including a plurality of Field Effect Transistor (FET) connected together into one or more circuits, said IC comprising:
a plurality of silicon islands in a surface silicon layer of a Silicon On Insulator (SOI) wafer, said silicon islands being defined and separated from each other by shallow trench isolation (STI) through a surface silicon layer to a buried oxide layer;
a FET having a metal gate on at least one said silicon island, each said FET being a metal gate FET comprising a silicon channel, a hi-k dielectric layer on said silicon channel, and a metal gate on said a hi-K dielectric layer;
one or more FET having a polysilicon gate on one or more other said silicon island, each said FET being a silicon gate FET comprising a silicon channel, a gate oxide layer on said silicon channel, and a polysilicon gate above said gate oxide layer;
a gate silicide layer on each polysilicon gate;
Silicon Germanium (SiGe) source/drains at each FET;
a source/drain silicide layer on each SiGe source/drain;
wiring to the silicide layers and metal gates connecting FETs together into one or more IC circuits; and
at least one fuse in one circuit of said one or more IC circuits, said at least one fuse comprising:
a polysilicon segment on oxide, an upper surface of said oxide being coplanar with an upper surface of an adjacent island,
a silicide layer on said polysilicon segment, and
contacts at opposite ends of said silicide layer, said wiring connecting said at least one fuse into one circuit, the presence of said fuse placing said one circuit in a first state, and opening said fuse placing said one circuit in a second state.
18 . A IC as in claim 17 , wherein at least one said silicon gate FET being a P-type FET (PFET),
wherein one or more of said silicon gate FETs further comprise an electrolytic layer on said gate oxide layer, said polysilicon gate being on said electrolytic layer, at least one polysilicon gate being on said gate oxide layer, and
wherein said high-k dielectric is selected from Zirconium Oxide (ZrO 5 ) and hafnium dioxide (HfO 2 ), said metal gate includes a work function metal selected from Aluminum (Al), Titanium Nitride (TiNi), and Titanium Aluminum (TiAl), said gate silicide layer is cobalt silicide (CoSi), said source/drain silicide layer is Nickel silicide (NiSi) source/drain layer on each SiGe source/drain, and said further comprises a tungsten pad on each said NiSi source/drain layer, said wiring connecting to the tungsten pads.
19 . An IC as in claim 18 , wherein said gate oxide layer in one or more of said silicon gate FETs is thicker than other silicon gate FETs in said IC and at least one said silicon gate FET is a P-type FET (PFET).