IP Library Granted Patent US 10,134,742
Granted Patent B2
US 10,134,742 · App. 14/663,878 · Granted Nov 20, 2018

Semiconductor device including a semiconductor substrate, a pillar, and a beam

Inventor: Takeshi Kishida (Tokyo, JP)
Assignee: Micron Technology, Inc.
H01L27/10897H01L27/10814H01L27/10835H01L27/10852
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,134,742
App. No.
14/663,878
Granted
Nov 20, 2018
Kind
B2
Abstract

The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion extending in a horizontal direction to support the lower electrode and a second portion that is vertically extended along the exterior wall of the electrode from the first portion.

Claims (23)

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of conductive pillars provided over the semiconductor substrate, the pillars having laterally-outer conductive side surfaces;

a dielectric structure spaced vertically above the semiconductor substrate, the dielectric structure comprising an opening extending vertically there-though and contacting the laterally-outer conductive side surfaces of all of the pillars, the dielectric structure comprising a horizontally-extending first dielectric member that horizontally-extends to the opening, the dielectric structure comprising a second dielectric member that contacts the first dielectric member adjacent the opening and that contacts the laterally-outer conductive side surfaces of only some of the pillars, the second dielectric member extending and projecting vertically from the first dielectric member adjacent the opening, the second dielectric member having a greater maximum vertical thickness than a minimum vertical thickness of the first dielectric member, the second dielectric member having a minimum lateral thickness that is greater than the minimum vertical thickness of the first dielectric member; and

the pillars being hollow, the dielectric structure only being outside the hollow pillars.

2. The semiconductor device of claim 1 , wherein the second dielectric member projects upwardly.

3. The semiconductor device of claim 1 , wherein the second dielectric member projects downwardly.

4. The semiconductor device of claim 1 , wherein the second dielectric member projects upwardly and downwardly.

5. The semiconductor device of claim 1 , wherein the first and second dielectric members comprise silicon nitride.

6. The semiconductor device of claim 1 , wherein the semiconductor device comprises a memory device comprising memory cells individually comprising a capacitor, the pillars individually comprising a storage electrode of the individual capacitors of the individual memory cells.

7. The semiconductor device of claim 1 , wherein the first dielectric member comprises silicon nitride.

8. The semiconductor device of claim 1 , wherein the second dielectric member comprises silicon nitride.

9. The semiconductor device of claim 1 , wherein the second dielectric member projects upwardly and contacts another structure that is above the dielectric structure.

10. The semiconductor device of claim 9 , wherein the another structure is dielectric.

11. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of conductive pillars provided over the semiconductor substrate, the pillars having laterally-outer conductive side surfaces; and

a dielectric structure spaced vertically above the semiconductor substrate, the dielectric structure comprising an opening extending vertically there-though and contacting the laterally-outer conductive side surfaces of all of the pillars, the dielectric structure comprising a horizontally-extending first dielectric member that horizontally-extends to the opening, the dielectric structure comprising a second dielectric member that contacts the first dielectric member adjacent the opening and that contacts the laterally-outer conductive side surfaces of only some of the pillars, the second dielectric member extending and projecting vertically from the first dielectric member adjacent the opening, the second dielectric member having a greater maximum vertical thickness than a minimum vertical thickness of the first dielectric member, the conductive pillars individually having a conductive uppermost surface, the second dielectric member having a dielectric uppermost surface that is downward of the conductive uppermost surface of the individual conductive pillars.

12. A memory device comprising memory cells individual comprising a capacitor, comprising:

a semiconductor substrate;

a plurality of conductive pillars provided over the semiconductor substrate, the pillars having laterally-outer conductive side surfaces, the pillars individually comprising a storage electrode of the individual capacitors of the individual memory cells;

a dielectric structure spaced vertically above the semiconductor substrate, the dielectric structure comprising an opening extending vertically there-though and contacting the laterally-outer conductive side surfaces of all of the pillars, the dielectric structure comprising a horizontally-extending first dielectric member that horizontally-extends to the opening, the dielectric structure comprising a second dielectric member that contacts the first dielectric member adjacent the opening and that contacts the laterally-outer conductive side surfaces of only some of the pillars, the second dielectric member extending and projecting vertically from the first dielectric member adjacent the opening, the second dielectric member having a greater maximum vertical thickness than a minimum vertical thickness of the first dielectric member; and

the second dielectric member having a dielectric uppermost surface and a laterally-outer side surface extending downwardly from the dielectric uppermost surface, the capacitors comprising a capacitor dielectric material that is over and contacts the dielectric uppermost surface of the second dielectric member and contacts the laterally-outer side surface of the second dielectric member.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2015
From: KISHIDA, TAKESHI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 035262/0247 →
Priority Claims (1)
JP 2014-072115 · Mar 31, 2014 · national
Continuity (1)
Related Publication 20150279845A1 · Oct 1, 2015