IP Library › Granted Patent US 9,892,053
Granted Patent B2
US 9,892,053 · App. 14/666,756 · Granted Feb 13, 2018

Compaction for memory hierarchies

Inventors: Jim K. Nilsson (Lund, SE); Tomas G. Akenine-Moller (Lund, SE); Franz P. Clarberg (Lund, SE)
Assignee: Intel Corporation
G06F12/0893G06F12/0897G06F12/023G06F2212/1021G06F2212/1044G06F2212/302G06F2212/401G06F2212/455
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Quick Facts
Patent No.
US 9,892,053
App. No.
14/666,756
Granted
Feb 13, 2018
Kind
B2
Abstract

In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.

Claims (40)

1. A method comprising:

providing a near and far memory coupled to a processor, wherein said near memory is faster than said far memory and said near memory is backed by said far memory;

compressing data to be stored in said near memory using a codec;

compacting said compressed data only in response to an indication that free memory is needed;

storing said compacted data so that said compressed and compacted data's footprint is less than that of compressed data before compaction; and

providing a buffer between said codec and said near memory, said buffer to store compressed data for said codec, such that said compressed data in said buffer has a smaller footprint than the compressed data from the codec.

2. The method of claim 1 including compacting before storing compressed data in the near memory.

3. The method of claim 1 including compacting a plurality of blocks of cache lines together as an addressable group.

4. The method of claim 1 including determining whether a plurality of cache lines can be stored as a contiguous block and if so storing said block contiguously in near memory.

5. The method of claim 4 including storing said block as an integer multiple of a cache line size in the near memory.

6. The method of claim 5 including providing an indication that said block as stored is compacted.

7. The method of claim 6 including reading data from said near memory by determining from said indication whether said block is compacted and if so decompacting said block and storing said decompacted chunk in said buffer as an integer multiple of a cache line size.

8. The method of claim 1 including compacting said data in the near memory.

9. The method of claim 8 including compacting a selected range of memory pages.

10. The method of claim 8 including storing a compacted range of page addresses in an address translation table.

11. The method of claim 8 including storing an indication that the range of pages have been compacted.

12. The method of claim 8 including compacting using an independent software that can be run at arbitrary points in time.

13. The method of claim 1 including storing both compacted and uncompacted compressed data in near memory.

14. The method of claim 1 including compressing then decompacting on writing to the near memory and reading data by decompacting then decompressing.

15. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising:

providing a near and far memory coupled to a processor, wherein said near memory is faster than said far memory and said near memory is backed by said far memory;

compressing data to be stored in said near memory using a codec;

compacting said compressed data only in response to an indication that free memory is needed;

storing said compacted data so that said compressed and compacted data's footprint is less than that of compressed data before compaction; and

providing a buffer between said codec and said near memory, said buffer to store compressed data for said codec, such that said compressed data in said buffer has a smaller footprint than the compressed data from the codec.

16. The media of claim 15 , said sequence including compacting before storing compressed data in the near memory.

17. The media of claim 15 , said sequence including compacting a plurality of blocks of cache lines together as an addressable group.

18. The media of claim 15 , said sequence including determining whether a plurality of cache lines can be stored as a contiguous block and if so storing said block contiguously in near memory.

19. The media of claim 18 , said sequence including storing said block as an integer multiple of a cache line size in the near memory.

20. The media of claim 19 , said sequence including providing an indication that said block as stored is compacted.

21. The media of claim 20 , said sequence including reading data from said near memory by determining from said indication whether said block is compacted and if so decompacting said block and storing said decompacted chunk in said buffer as an integer multiple of a cache line size.

22. An apparatus comprising:

a processor;

a near and far memory coupled to the processor, wherein said near memory is faster than said far memory and said near memory is backed by said far memory;

a codec to compress data to be stored in said near memory;

said processor to compact said compressed data only in response to an indication that free memory is needed and store said compacted data so that said compressed and compacted data's footprint is less than that of compressed data before compaction, and provide a buffer between said codec and said near memory, said buffer to store compressed data for said codec, such that said compressed data in said buffer has a smaller footprint than the compressed data from the codec.

23. The apparatus of claim 22 , said codec to compact before storing compressed data in the near memory.

24. The apparatus of claim 22 , said codec to compact a plurality of blocks of cache lines together as an addressable group.

25. The apparatus of claim 22 , said processor to determine whether a plurality of cache lines can be stored as a contiguous block and if so storing said block contiguously in near memory.

26. The apparatus of claim 25 , said processor to store said block as an integer multiple of a cache line size of the near memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2015
From: NILSSON, JIM K.; AKENINE-MOLLER, TOMAS G.; CLARBERG, FRANZ P.
To: INTEL CORPORATION
Reel/Frame 035707/0725 →
Continuity (1)
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