Semiconductor package

1. A stacked semiconductor package, comprising:

a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and

a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package;

wherein:

the first semiconductor package further includes:

a sealing resin sealing the first semiconductor element;

a conductive layer located in contact with the sealing resin and located above the first semiconductor element and located in a region above a region between two ends of the first semiconductor element; and

a thermal via connected to the conductive layer and located on the first circuit board in an area where the first semiconductor is not located, the conductive layer and thermal via configured to allow heat generated from the first semiconductor element to escape below the first semiconductor package.

2. A stacked semiconductor package according to claim 1 , wherein the conductive layer is located on the sealing resin.

3. A stacked semiconductor package according to claim 2 , wherein:

the first semiconductor package includes a plurality of joining electrode terminals joined with the second semiconductor package and located around the first semiconductor element; and

the conductive layer is located inner to the plurality of joining electrode terminals.

4. A stacked semiconductor package according to claim 1 , wherein the conductive layer is formed of copper or a copper alloy.

5. A stacked semiconductor package according to claim 2 , wherein:

the first semiconductor package includes a plurality of joining electrode terminals joined with the second semiconductor package and located around the first semiconductor element; and

the thermal via is located inner to the plurality of joining electrode terminals.

6. A stacked semiconductor package according to claim 2 , wherein the plurality of joining electrode terminals each include a resin core ball.

7. A stacked semiconductor package according to claim 2 , wherein the conductive layer is located also at side surfaces of the first semiconductor package.

8. A stacked semiconductor package according to claim 1 , wherein the conductive layer is covered with the sealing resin.

9. A stacked semiconductor package according to claim 8 , wherein the conductive layer is located on the first semiconductor element with an adhesive or a space being sandwiched therebetween.

10. A stacked semiconductor package according to claim 2 , wherein the conductive layer is a wiring board including at least two layers.

11. A stacked semiconductor package according to claim 10 , wherein:

a via is located in the wiring board including at least two layers and in the sealing resin; and

the first circuit board and the second circuit board are electrically connected to each other by the via.

12. A stacked semiconductor package according to claim 10 , wherein:

a via is located in the sealing resin; and

the first circuit board and the second circuit board are electrically connected to each other by the via and a circuit of the wiring board including at least two layers.

13. A stacked semiconductor package according to claim 5 , wherein the thermal via is located inside the first circuit board.

14. A stacked semiconductor package according to claim 1 , wherein:

the first semiconductor package further includes two pads attached to the first semiconductor element; and

the conductive layer is located in a region above a region between the two pads.

15. A stacked semiconductor package according to claim 1 , wherein the conductive layer is located above the first semiconductor element to cover the entire first semiconductor element.