Method for verifying design rule checks
View Patent ↗A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.
1. A method for design rule verification, the method comprising:
providing a design rule check deck based on a design rule manual (DRM) having a plurality of design rules;
providing a plurality of primitive objects;
creating a plurality of collection objects, each collection object using one or more primitive objects;
using the plurality of collection objects, creating a plurality of DRM test cases;
assigning names to each of the plurality of DRM test cases, each of the names following a naming convention that includes a rule name of the plurality of design rules and an expected pass or fail indication within each of the names;
using the plurality of named DRM test cases to verify the design rule check deck; and
manufacturing an integrated circuit based on the verified design rule check deck.
2. The method of claim 1 , further comprising organizing the plurality of named DRM test cases into a combined database file after assigning names to each of the plurality of DRM test cases.
3. The method of claim 2 , further comprising running the design rule check deck on the DRM test cases in the combined database file.
4. The method of claim 3 , further comprising outputting an error database file as a result of running the design rule check deck on the design rule manual test cases in the combined database file.
5. The method of claim 4 , further comprising:
merging the error database file with the combined database file; and
identifying any unintentional failures in the error database file.
6. The method of claim 5 , further comprising:
determining that there is an unintentional error in the error database file;
modifying the design rule check deck or test cases to correct the unintended failure;
running the modified design rule check deck and test cases;
outputting another error database file merged with the combined database file;
identifying that there are no other unintentional failures; and
determining that the design rule check deck is verified.
7. The method of claim 6 , wherein the verified design rule check deck is used to create a design rule compliant physical layout for an integrated circuit.
8. The method of claim 1 , wherein providing a plurality of primitive objects comprises providing one or more of a square, rectangle, L-shape, or bevel shape.
9. The method of claim 1 , wherein creating a plurality of DRM test cases comprises creating a test case for verifying that an edge spacing between two shapes is greater than or equal to a minimum spacing.
10. A method for design rule verification, the method comprising:
providing a design rule check deck based on a design rule manual (DRM) having a plurality of design rules;
providing a plurality of primitive objects;
creating a plurality of collection objects, each collection object using one or more primitive objects;
using the plurality of collection objects, creating a plurality of DRM test cases;
assigning names to each of the plurality of DRM test cases, each of the names following a naming convention that includes a rule name of the plurality of design rules and an expected pass or fail indication within each of the names;
organizing the plurality of named DRM test cases into a combined database file;
running the design rule check deck on the named DRM test cases in the combined database file;
outputting an error database file as a result of running the design rule check deck on the design rule manual test cases in the combined database file;
merging the error database file with the combined database file;
identifying any unintentional failures in the error database file;
correcting the errors set out in the error database file;
determining that the design rule check deck is verified; and
manufacturing an integrated circuit based on the verified design rule check deck.
11. The method of claim 10 , wherein outputting an error database file and correcting the errors set out in the error database file further comprises:
determining that there is an unintentional error in the error database file;
modifying the design rule check deck or test cases to correct the unintended failure;
running the modified design rule check deck and test cases;
outputting another error database file merged with the combined database file; and
identifying that there are no other unintentional failures.
12. The method of claim 10 , wherein the verified design rule check deck is used to create a design rule compliant physical layout for an integrated circuit.
13. The method of claim 10 , wherein providing a plurality of primitive objects comprises providing one or more of a square, rectangle, L-shape, or bevel shape.
14. The method of claim 10 , wherein creating a plurality of DRM test cases comprises creating a test case for verifying that an edge spacing between two objects is greater than or equal to a minimum spacing.
15. The method of claim 10 , wherein creating a plurality of DRM test cases comprises creating a test case for verifying that a corner-to-corner spacing between two objects is greater than or equal to a minimum spacing.
16. A method for design rule verification, the method comprising:
providing a design rule check deck based on a design rule manual (DRM) having a plurality of design rules;
providing a plurality of primitive objects;
creating a plurality of collection objects, each collection object using one or more primitive objects;
using the plurality of collection objects, creating a plurality of DRM test cases;
assigning names to each of the plurality of DRM test cases, each of the names following a naming convention that includes a rule name of the plurality of design rules and an expected pass or fail indication within each of the names;
organizing the plurality of named DRM test cases into a combined database file;
running the design rule check deck on the named DRM test cases in the combined database file;
determining that there is at least one unintentional error in the error database file;
modifying the design rule check deck or test cases to correct the at least one unintended failure;
running the modified design rule check deck and test cases;
outputting another error database file merged with the combined database file;
identifying that there are no other unintentional failures;
correcting the errors set out in the error database file;
determining that the design rule check deck is verified; and
manufacturing an integrated circuit based on the verified design rule check deck.
17. The method of claim 16 , wherein the verified design rule check deck is used to create a design rule compliant physical layout for an integrated circuit.
18. The method of claim 16 , wherein providing a plurality of primitive objects comprises providing one or more of a square, rectangle, L-shape, or bevel shape.
19. The method of claim 16 , wherein creating a plurality of DRM test cases comprises creating a test case for verifying that an edge spacing between two objects is greater than or equal to a minimum spacing.
20. The method of claim 16 , wherein creating a plurality of DRM test cases comprises creating a test case for verifying that a corner-to-corner spacing between two objects is greater than or equal to a minimum spacing.