Single level cell write buffering for multiple level cell non-volatile memory

1. An apparatus comprising:

non-volatile memory to include a first region in a Single Level Cell (SLC) mode, a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is to be unexposed as user addressable space; and

logic to move a portion of the second region from the multiple level cell mode to the SLC mode, wherein the portion of the second region is capable to enter into the SLC mode based on status of at least one bit, wherein each time one or more new blocks are opened for writing, they are to be opened in SLC mode and once a write idle threshold is met, content from one or more SLC blocks are to be garbage collected to one or more MLC blocks, wherein burst write operations are to be directed at the second region in response to a threshold number of burst write operations directed at the first region.

2. The apparatus of claim 1 , wherein data written to the portion of the second region is to be moved to the first region during an idle time between write operations directed at the non-volatile memory.

3. The apparatus of claim 1 , comprising logic to move one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

4. The apparatus of claim 1 , wherein burst write operations are to be directed at the first region.

5. The apparatus of claim 1 , wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

6. The apparatus of claim 1 , wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.

7. The apparatus of claim 1 , wherein the non-volatile memory is to comprise one of: nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

8. The apparatus of claim 1 , wherein an SSD is to comprise the non-volatile memory and the logic.

9. The apparatus of claim 1 , wherein the third region is to store data for garbage collection.

10. The apparatus of claim 1 , wherein data written to non-volatile memory is to be written to the first region in the SLC mode, wherein the written data to the first region in the SLC mode is to be moved to the second region during an idle time between write operations directed at the non-volatile memory.

11. The apparatus of claim 1 , wherein the logic is to move the portion of the second region from the multiple level cell mode to the SLC mode without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.

12. A method comprising:

partitioning non-volatile memory to include a first region in a Single Level Cell (SLC) mode, a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is unexposed as user addressable space; and

moving a portion of the second region from the multiple level cell mode to the SLC mode, wherein the portion of the second region is capable to enter into the SLC mode based on status of at least one bit, wherein each time one or more new blocks are opened for writing, they are opened in SLC mode and once a write idle threshold is met, content from one or more SLC blocks are garbage collected to one or more MLC blocks, wherein burst write operations are directed at the second region in response to a threshold number of burst write operations directed at the first region.

13. The method of claim 12 , further comprising moving data written to the portion of the second region to the first region during an idle time between write operations directed at the non-volatile memory.

14. The method of claim 12 , further comprising moving one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

15. The method of claim 12 , further comprising directing burst write operations at the first region.

16. The method of claim 12 , wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

17. The method of claim 12 , wherein the non-volatile memory comprises one of: nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

18. A system comprising:

non-volatile memory; and

at least one processor core to access the non-volatile memory;

the non-volatile memory to include a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell (MLC) mode, and a third region in the MLC mode, wherein the third region is to be unexposed as user addressable space; and

logic to move a portion of the second region from the multiple level cell mode to the SLC mode, wherein the portion of the second region is capable to enter into the SLC mode based on status of at least one bit, wherein each time one or more new blocks are opened for writing, they are to be opened in SLC mode and once a write idle threshold is met, content from one or more SLC blocks are to be garbage collected to one or more MLC block, wherein burst write operations are to be directed at the second region in response to a threshold number of burst write operations directed at the first region.

19. The system of claim 18 , wherein data written to the portion of the second region is to be moved to the first region during an idle time between write operations directed at the non-volatile memory.

20. The system of claim 18 , comprising logic to move one or more portions of the second region from the multiple level cell mode to the SLC mode to create the first region.

21. The system of claim 18 , wherein burst write operations are to be directed at the first region.

22. The system of claim 18 , wherein the multiple level cell mode is a Three Level Cell (TLC) mode.

23. The system of claim 18 , wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.

24. The system of claim 18 , wherein the non-volatile memory is to comprise one of: nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, Phase Change Memory (PCM), and byte addressable 3-Dimensional Cross Point Memory.

25. The system of claim 18 , wherein an SSD is to comprise the non-volatile memory and the logic.