IP Library Granted Patent US 9,680,003
Granted Patent B2
US 9,680,003 · App. 14/671,590 · Granted Jun 13, 2017

Trench MOSFET shield poly contact

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Quick Facts
Patent No.
US 9,680,003
App. No.
14/671,590
Granted
Jun 13, 2017
Kind
B2
Abstract

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench.

Claims (31)

1. A device comprising:

a plurality of vertical transistors at a semiconductor layer coupled together in parallel residing within an outer perimeter of a recessed region of a semiconductor layer, each vertical transistor comprising a mesa having a channel region and being spaced apart from corresponding adjacent mesas in a transverse direction by a first dimension, each corresponding mesa spaced apart from the outer perimeter in a lateral direction by approximately the first dimension;

each adjacent mesa pair associated with a point that is equidistant from an end of each mesa of the adjacent mesa pair and from the outer perimeter in the lateral direction; and

a plurality of inter-level conductive plugs connected to a shield terminal electrode and to a device shield within the recessed region, each point being associated with a corresponding mesa pair and located within a perimeter of a corresponding one of the plurality of conductive plugs.

2. The device of claim 1 , wherein between each mesa of each of the mesa pairs there is an active gate corresponding to channel regions of each mesa, and an active shield portion of the device shield.

3. The device of claim 2 , wherein the device shield further comprises a termination shield that is concentric to the outer perimeter, and each end of a plurality of active shields is connected to opposing sides of the termination shield.

4. The device of claim 3 , wherein a transverse dimension each conductive plug is equal to or less than a transverse dimension of a width of the active shield.

5. The device of claim 4 , wherein each conductive plug is spaced apart from all edges of the device shield by a dimension that is at least one-half of a lateral dimension of the conductive plug.

6. The device of claim 1 , wherein each conductive plug is spaced apart from all edges of the device shield by a dimension that is at least one-half of a lateral dimension of the conductive plug.

7. The device of claim 1 , wherein the device shield further comprises a termination shield that is concentric to the outer perimeter, and each end of a plurality of active shields is connected to opposing sides of the termination shield.

8. The device of claim 1 , wherein approximately the first dimension is +/−25% of the first dimension.

9. The device of claim 1 , wherein approximately the first dimension is +/−10% of the lateral dimension of the conductive plugs.

10. The device of claim 1 , wherein approximately the first dimension is based upon a manufacturing tolerance of a process used to manufacture the device.

11. The device of claim 1 , wherein each conductive plug has a minimum diameter and a center location, and each point is within an offset dimension of the center location of its corresponding conductive plug, wherein the offset dimension is approximately 25% of the minimum diameter.

12. The device of claim 1 , wherein each conductive plug has a minimum diameter and a center location, and each point is within an offset dimension of the center location of its corresponding conductive plug, wherein the offset dimension is at least 10% of the minimum diameter.

13. A device comprising:

a semiconductor layer comprising a first major surface and a second major surface;

a plurality of mesa structures of the semiconductor layer defined by a recess of the semiconductor layer, the recess having an outer perimeter;

each mesa structure comprising

two lateral major sides and two minor sides, from a plan view, each major side having a first dimension, each minor side having a second dimension, the first dimension being at least twice the second dimension;

a first source/drain region;

a channel region, the channel region being further from the first major surface than the first source drain region

from the plan view, each pair of adjacent mesas comprises

a transverse spacing between mesas of the pair that is a third dimension, a lateral spacing between an end of each mesa and a proximal location of the outer perimeter that is a fourth dimension, the third and fourth dimensions being substantially the same dimension;

from the plan view, each pair of mesas defines a trench region of the recess comprising an active trench and a termination trench, the active trench residing between the pair of mesas, and the termination trench residing in a lateral direction between the end of each mesa and their corresponding active trench and the perimeter;

each trench region comprising

an active portion of a shield electrode that resides at the active trench of the trench region, and a termination portion residing at the termination trench of the trench region; and

a control electrode between the first major surface and a shield region to control a conductivity state of the channel region of each mesa of pair of mesas corresponding to the trench;

a shield termination electrode;

each shield electrode's termination region connected to a corresponding conductive plug that is further connected to a shield runner, and from the plan view, a perimeter of the conductive plug includes a point that is equidistant to an end of each mesa corresponding to the shield electrodes' pair of mesas and a proximal side of the outer perimeter.

14. The device of claim 13 , wherein each mesa structure further comprises a second source/drain, wherein the channel region is between the first and second source/drain.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0341 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0359 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0974 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0095 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0112 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2015
From: QIN, GANMING; DE FRESART, EDOUARD D.; KU, PON SUNG; PETRAS, MICHAEL F.; ZITOUNI, MOANISS; ZUPAC, DRAGAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 035278/0038 →