Method and apparatus for improving immunity to defects in a non-volatile memory
View Patent ↗Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.
1. An apparatus comprising:
non-volatile memory to store user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes; and
logic to rotate the user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes to match a mapping of the parity data, wherein both the user data and the parity data are to be dispatched in a granularity of quad-plane pages, wherein the quad-plane pages are to be aligned to a flat indirection unit for Varied-Sector-Size (VSS) or Non-VSS implementations.
2. The apparatus of claim 1 , wherein the logic is to rotate the user data to match the mapping of the parity data by causing a plurality of pages of the user data and a page of the parity data to be stored in a first plane of the second set of the plurality of planes.
3. The apparatus of claim 2 , wherein the page of the parity data is to correspond to a different page of the user data than the plurality of the pages of the user data.
4. The apparatus of claim 1 , wherein the first set of the plurality of planes and the second set of the plurality of planes are to at least partially overlap in one of the plurality of dies.
5. The apparatus of claim 1 , wherein the second set of the plurality of planes is in one of the plurality of dies.
6. The apparatus of claim 1 , wherein the logic is to rotate the user data to match the mapping of the parity data to support a Varied-Sector-Size (VSS) implementation or a Non-VSS implementation in a flat indirection system.
7. The apparatus of claim 1 , wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.
8. The apparatus of claim 1 , wherein the non-volatile memory is to comprise one of: Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), Phase Change Memory (PCM), or flash memory.
9. The apparatus of claim 1 , wherein an SSD is to comprise the non-volatile memory and the logic.
10. The apparatus of claim 1 , wherein the non-volatile memory is to comprise one of: nanowire memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, and byte addressable 3-Dimensional Cross Point Memory.
11. A system comprising:
non-volatile memory; and
at least one processor core to access the non-volatile memory;
the non-volatile memory to store user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes; and
logic to rotate the user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes to match a mapping of the parity data, wherein both the user data and the parity data are to be dispatched in a granularity of quad-plane pages, wherein the quad-plane pages are to be aligned to a flat indirection unit for Varied-Sector-Size (VSS) or Non-VSS implementations.
12. The system of claim 11 , wherein the logic is to rotate the user data to match the mapping of the parity data by causing a plurality of pages of the user data and a page of the parity data to be stored in a first plane of the second set of the plurality of planes.
13. The system of claim 12 , wherein the page of the parity data is to correspond to a different page of the user data than the plurality of the pages of the user data.
14. The system of claim 11 , wherein the first set of the plurality of planes and the second set of the plurality of planes are to at least partially overlap in one of the plurality of dies.
15. The system of claim 11 , wherein the second set of the plurality of planes is in one of the plurality of dies.
16. The system of claim 11 , wherein the logic is to rotate the user data to match the mapping of the parity data to support a Varied-Sector-Size (VSS) implementation or a Non-VSS implementation in a flat indirection system.
17. The system of claim 11 , wherein the non-volatile memory, the logic, and a Solid State Drive (SSD) are on a same integrated circuit device.
18. The system of claim 11 , wherein the non-volatile memory is to comprise one of: Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), Phase Change Memory (PCM), or flash memory.
19. The system of claim 11 , wherein an SSD is to comprise the non-volatile memory and the logic.
20. A method comprising:
storing, in non-volatile memory, user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes; and
rotating the user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes to match a mapping of the parity data, wherein both the user data and the parity data are dispatched in a granularity of quad-plane pages, wherein the quad-plane pages are aligned to a flat indirection unit for Varied-Sector-Size (VSS) or Non-VSS implementations.
21. The method of claim 20 , further comprising rotating the user data to match the mapping of the parity data by causing a plurality of pages of the user data and a page of the parity data to be stored in a first plane of the second set of the plurality of planes.
22. The method of claim 21 , wherein the page of the parity data is to correspond to a different page of the user data than the plurality of the pages of the user data.
23. The method of claim 20 , further comprising at least partially overlapping the first set of the plurality of planes and the second set of the plurality of planes in one of the plurality of dies.
24. The method of claim 20 , wherein the second set of the plurality of planes is in one of the plurality of dies.
25. The method of claim 20 , further comprising to rotating the user data to match the mapping of the parity data to support a Varied-Sector-Size (VSS) implementation or a Non-VSS implementation in a flat indirection system.
26. The method of claim 20 , wherein the non-volatile memory comprises one of: Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), Phase Change Memory (PCM), or flash memory.