Method, apparatus, and system for unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded processor environment
View Patent ↗Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.
1. A method comprising:
masking one or more thread requests;
executing at least one of a command routine or a command thread for a command in response to both ascertaining that a ceasing of all bus activity for the one or more masked thread requests has occurred, and additionally ascertaining that a completion of all routines being processed for the one or more masked thread requests has occurred, wherein
the command routine or the command thread reads a plurality of parameters using thread atomicity with deterministic synchronization, and
the plurality of parameters comprises one or more of a counter and a state indicator.
2. The method of claim 1 further comprising selecting the one or more thread requests for masking by monitoring thread activity for each of a plurality of threads.
3. The method of claim 1 , further comprising:
obtaining a set of one or more samples of the at least one state or counter, wherein after sampling a first parameter of the plurality of parameters, a subsequent sampling of a second parameter of the plurality of parameters is performed without any thread changing any of the plurality of parameters.
4. The method of claim 1 further comprising processing the command using a reduced instruction set computer (RISC) configured with a dedicated command thread for executing the command.
5. The method of claim 4 further comprising using a first register for issuing the command to the RISC, and using a second register for identifying one or more threads that are attributed to the command.
6. The method of claim 1 further comprising generating a completion notification.
7. The method of claim 1 further comprising transmitting the plurality of parameters to an application to provide the application with at least one of an unambiguous counter reading or an unambiguous state indication.
8. An apparatus configured to perform parameter sampling in a heterogeneous multi-core or multi-threaded environment, the apparatus comprising:
a processing mechanism including a central processing unit (CPU) and a RISC complex, wherein the processing mechanism is configured for masking one or more thread requests; and
a scheduler, operatively coupled to the CPU of the processing mechanism by a bus, wherein
the processing mechanism is configured for executing a command in response to the scheduler determining both that a ceasing of activity on the bus for the one or more masked thread requests has occurred, and that a completion of all routines being processed for the one or more masked thread requests has occurred,
the processing mechanism is configured to execute at least one of a command routine or a command thread for the command,
the command routine or the command thread reads a plurality of parameters using thread atomicity with deterministic synchronization, and
the plurality of parameters comprises one or more of a counter and a state indicator.
9. The apparatus of claim 8 wherein the scheduler is configured to select one or more thread requests for masking by monitoring thread activity for each of a plurality of threads.
10. The apparatus of claim 8 wherein the processing mechanism is further configured to perform masking by masking a plurality of thread requests while executing a redundancy protocol, such that at least one state or counter is sampled in an unambiguous manner.
11. The apparatus of claim 8 wherein the processing mechanism is further configured to process the command using a dedicated command thread that executes the command and reads at least one state or counter.
12. The apparatus of claim 8 further comprising a first register, operatively coupled to the processing mechanism, for issuing the command to the processing mechanism.
13. The apparatus of claim 12 , further comprising at least a second register and a third register, for identifying one or more threads that are attributed to the command.
14. The apparatus of claim 8 wherein the processing mechanism is further configured to generate a completion notification in response to the command being executed.
15. The apparatus of claim 8 wherein the processing mechanism is further configured to transmit the plurality of parameters to an application to provide the application with at least one of an unambiguous counter reading or an unambiguous state indication.
16. The apparatus of claim 8 wherein the apparatus is provided in the form of one or more integrated circuits.
17. A system configured to perform parameter sampling in a heterogeneous multi-core or multi-threaded environment, the system comprising:
a central processing unit (CPU);
a RISC complex;
a scheduler; and
a bus, operatively coupled to the scheduler;
wherein the scheduler is configured for executing a command only in response to any threads related to or attributed to the command not being currently executed;
upon commencement of executing the command, the scheduler being configured to use thread atomicity with deterministic synchronization to not allow any threads other than a command thread to be processed until the command completes; wherein the command is configured for reading one or more of a counter and a state indicator.
18. The system of claim 17 wherein the synchronously read plurality of states or the synchronously read plurality of counters are provided to an application.
19. The system of claim 17 further comprising:
a processor operatively coupled to the scheduler;
wherein the processor is configured for processing the command in response to the scheduler determining both: (a) activity on the bus ceasing for the one or more masked thread requests, and (b) completion of all routines being processed for the one or more masked threads;
wherein the processor is configured to process the command by executing at least one of a command routine or the command thread for the command;
wherein the command routine or the command thread synchronously reads a plurality of parameters comprising one or more of a counter and a state indicator;
wherein the processor is further configured for receiving a command, and for masking one or more thread requests.
20. The system of claim 19 wherein the processor is further configured to provide the synchronously read plurality of states or the synchronously read plurality of counters to an application.