IP Library Granted Patent US 9,269,608
Granted Patent B2
US 9,269,608 · App. 14/673,309 · Granted Feb 23, 2016

Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,269,608
App. No.
14/673,309
Granted
Feb 23, 2016
Kind
B2
Abstract

A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC or SiGeBC layer as an etch stop. In some embodiments, the SiGeC or SiGeBC layer is formed by epitaxial growth, ion implantation or a combination of epitaxial growth and ion implantation.

Claims (52)

1. A method comprising:

forming a first wafer having a first bonding material;

forming a second wafer having a substrate, a SiGeBC layer, an active layer and a second bonding material, the active layer being between the SiGeBC layer and the second bonding material;

bonding the second wafer to the first wafer at the first and second bonding materials; and

removing the substrate using the SiGeBC layer as an etch stop.

2. The method of claim 1 , wherein:

the forming of the second wafer includes forming the SiGeBC layer by epitaxial growth.

3. The method of claim 1 , wherein:

the forming of the second wafer includes forming the SiGeBC layer by ion implantation.

4. The method of claim 1 , wherein:

the forming of the second wafer includes forming the SiGeBC layer by a combination of epitaxial growth and ion implantation.

5. The method of claim 1 , wherein:

the SiGeBC layer induces a strain in at least a portion of the active layer.

6. The method of claim 1 , further comprising:

removing the SiGeBC layer.

7. The method of claim 1 , wherein:

the forming of the second wafer includes forming the SiGeBC layer and the active layer prior to the bonding of the second wafer to the first wafer.

8. The method of claim 1 , wherein:

the second wafer is a bulk silicon wafer.

9. The method of claim 1 , wherein:

the active layer includes a gate and a channel; and

the bonding of the second wafer to the first wafer causes the gate to be between the channel and the first wafer.

10. The method of claim 1 , wherein:

the forming of the first wafer includes forming a trap rich layer therein.

11. A method comprising:

forming a first wafer having a first bonding material;

forming a second wafer having a substrate, an etch stop layer, an active layer and a second bonding material, the active layer being between the etch stop layer and the second bonding material, the etch stop layer comprising silicon, germanium, and carbon;

bonding the second wafer to the first wafer at the first and second bonding materials; and

removing the substrate using the etch stop layer.

12. The method of claim 11 , further comprising:

forming the etch stop layer by epitaxial growth of the silicon, germanium, and carbon.

13. The method of claim 11 , further comprising:

forming the etch stop layer by ion implantation of the silicon, germanium, and carbon.

14. The method of claim 11 , further comprising:

forming the etch stop layer by a combination of epitaxial growth and ion implantation of the silicon, germanium, and carbon.

15. The method of claim 11 , further comprising:

removing the etch stop layer.

16. The method of claim 11 , further comprising:

forming the etch stop layer and the active layer within the second wafer prior to bonding the first wafer to the second wafer.

17. A semiconductor structure comprising:

a first wafer;

a first bonding material at a surface of the first wafer;

a second wafer bonded to the first wafer;

an active layer within the second wafer; and

a second bonding material at a surface of the second wafer and being bonded to the first bonding material;

wherein a substrate has been removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeBC layer as an etch stop.

18. The semiconductor structure of claim 17 , further comprising:

the SiGeBC layer as also a strain-inducing layer.

19. The semiconductor structure of claim 17 , wherein:

the second wafer is a bulk silicon wafer prior to formation of the active layer and the SiGeBC layer therein.

20. The semiconductor structure of claim 17 , wherein:

the active layer includes a gate and a channel, the gate being between the channel and the first wafer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2015
From: FANELLI, STEPHEN A.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 035291/0088 →