Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
1. A method for forming a semiconductor device comprising:
providing a stressed silicon-on-insulator (SOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions, the first stressed semiconductor portion defining a first active region;
replacing the second stressed semiconductor portion with another semiconductor portion comprising a first semiconductor material; and
driving a second semiconductor material into the first semiconductor material of the other semiconductor portion defining a second active region.
2. The method according to claim 1 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon and germanium.
3. The method according to claim 1 further comprising forming a mask layer over the first stressed semiconductor portion before replacing the second stressed semiconductor portion with the other semiconductor portion.
4. The method according to claim 1 wherein replacing the second stressed semiconductor portion with the other semiconductor portion comprises:
removing the second stressed semiconductor portion except for a second stressed semiconductor portion bottom layer; and
forming the other semiconductor portion on the second stressed semiconductor portion bottom layer.
5. The method according to claim 4 further comprising annealing the second stressed semiconductor portion bottom layer before forming the other semiconductor portion.
6. The method according to claim 4 further comprising annealing the other semiconductor portion.
7. The method according to claim 1 wherein driving the second semiconductor material into the first semiconductor material comprises:
forming a second semiconductor layer comprising the second semiconductor material over the other semiconductor portion; and
oxidizing the second semiconductor layer to drive the second semiconductor material into the first semiconductor material.
8. The method according to claim 1 further comprising:
forming first and second gate stacks over the first and second active regions, respectively;
forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and
forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.
9. The method according to claim 8 wherein the first channel region is for an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a FinFET structure, and the second channel region is for a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) having a FinFET structure.
10. The method according to claim 1 wherein the stressed SOI wafer comprises a fully depleted SOI (FDSOI) wafer.
11. The method according to claim 1 wherein the first active region is for an n-channel metal-oxide semiconductor field-effect transistor, and the second active region is for a p-channel metal-oxide semiconductor field-effect transistor.
12. A method for forming semiconductor device comprising:
providing a stressed silicon-on-insulator (SOI) wafer comprising a stressed silicon layer having first and second laterally adjacent stressed silicon portions, the first stressed silicon portion defining a first active region; and
driving silicon-germanium into another silicon portion associated with the second stressed silicon portion defining a second active region.
13. The method according to claim 12 further comprising:
forming a mask layer over the first stressed silicon portion; and
replacing the second stressed silicon portion with the other silicon portion.
14. The method according to claim 13 wherein replacing the second stressed silicon portion with the other silicon portion comprises:
removing the second stressed silicon portion except for a second stressed silicon portion bottom layer; and
forming the other silicon portion on the second stressed silicon portion bottom layer.
15. The method according to claim 14 further comprising annealing the second stressed silicon portion bottom layer before forming the other silicon portion.
16. The method according to claim 14 further comprising annealing the other silicon portion.
17. The method according to claim 13 wherein driving the silicon-germanium into the other silicon portion comprises:
forming a silicon-germanium layer over the other silicon portion; and
oxidizing the silicon-germanium layer to drive the silicon-germanium into the other silicon portion.
18. The method according to claim 12 further comprising:
forming first and second gate stacks over the first and second active regions, respectively;
forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and
forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.
19. The method according to claim 18 wherein the first channel region is for an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a FinFET structure, and the second channel region is for a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) having a FinFET structure.
20. The method according to claim 12 wherein the stressed SOI wafer comprises a fully depleted SOI (FDSOI) wafer.
21. The method according to claim 12 wherein the first active region is for an n-channel metal-oxide semiconductor field-effect transistor, and the second active region is for a p-channel metal-oxide semiconductor field-effect transistor.
22. A method for forming semiconductor device comprising:
providing a stressed silicon-on-insulator (SOI) wafer comprising a stressed silicon layer having first and second laterally adjacent stressed silicon portions, the first stressed silicon portion defining a first active region;
driving silicon-germanium into another silicon portion associated with the second stressed silicon portion defining a second active region;
forming first and second gate stacks over the first and second active regions, respectively;
forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and
forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.
23. The method according to claim 22 wherein the first active region is for an n-channel metal-oxide semiconductor field-effect transistor, and the second active region is for a p-channel metal-oxide semiconductor field-effect transistor.