Low energy accelerator processor architecture with short parallel instruction word
Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
1. An integrated circuit, comprising:
a system bus for transferring data between memory devices, processors, and peripheral devices having a data width N, where N is a positive integer;
a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and
a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory coupled to the system bus, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to a selected one of the data width N of the system bus and twice the data width N of the system bus;
wherein the instruction words for the low energy accelerator processor have a field of 11 bits containing opcodes for the load store unit.
2. The integrated circuit of claim 1 , wherein the low energy accelerator processor further comprises the multiply unit and the butterfly/adder ALU unit configured to execute fixed point instructions.
3. The integrated circuit of claim 1 , and further comprising a peripheral bridge unit coupled to the system bus and configured to communicate data to and from additional circuitry.
4. The integrated circuit of claim 1 , and further comprising additional circuitry comprising analog circuitry.
5. The integrated circuit of claim 4 , wherein the analog circuitry further comprises an analog to digital converter circuit.
6. The integrated circuit of claim 1 , wherein the instruction words stored for the low energy accelerator processor include instruction words configured to cause the low energy accelerator to perform vector computations.
7. The integrated circuit of claim 1 , wherein the low energy accelerator further comprises the multiply unit and the butterfly/adder ALU unit configured to perform vector operations in floating point and fixed point computations.
8. The integrated circuit of claim 7 , and further comprising an operand overload register containing a flag indicating a floating point computation.
9. The integrated circuit of claim 1 , wherein the instruction words for the low energy accelerator processor have a field of 1 bits containing opcodes for the load coefficient unit.
10. The integrated circuit of claim 1 , wherein the instruction words for the low energy accelerator processor have a field of 6 bits for the multiply unit.
11. The integrated circuit of claim 1 , wherein the instruction words for the low energy accelerator processor have a field of 13 bits for the butterfly/adder ALU unit.