Integrated structures of vertically-stacked memory cells
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
1. An integrated structure, comprising:
a stack of alternating silicon dioxide levels and conductively-doped silicon levels;
an opening extending through the stack, the opening having opening sidewalls along edges of the silicon dioxide levels;
edges of the conductively-doped silicon levels being laterally recessed relative to the edges of the silicon dioxide levels to define cavities located between the silicon dioxide levels; the cavities extending from the opening sidewalls into the conductively-doped silicon levels;
regions of the silicon dioxide levels over and under the cavities being ledges of the silicon dioxide levels separating adjacent cavities from one another; the ledges being thinned relative to regions of the silicon dioxide levels not encompassed by the ledges, each of the ledges terminating in a La region having rounded edge along the opening sidewalls, the tip region being outwardly curved along its entirety;
charge-blocking dielectric within the cavities;
charge-storage structures within the opening and extending within the cavities, the charge-storage structures having continuous curved outer peripheries;
dielectric material within the openings and extending along the charge-storage structures;
channel material within the openings along the dielectric material;
wherein the conductively-doped silicon levels comprise control gates; wherein the charge-blocking dielectric is between the control gates and the charge-storage structures; wherein the charge-storage structures have gate lengths L 1 and the control gates have gate lengths L 2 ; and wherein L 1 and L 2 differ by less than 10 nm; and
wherein the charge-blocking dielectric comprises a first region containing silicon dioxide, a second region containing silicon nitride, and a third region containing oxide; with the second region being between the first and third regions.
2. The integrated structure of claim 1 wherein the regions of the silicon dioxide levels not encompassed by the ledges have thicknesses within a range of from about 20 nm to about 40 nm, and wherein the ledges have thicknesses within a range of from about 10 nm to about 15 nm.
3. The integrated structure of claim 1 wherein the ledges have thicknesses reduced relative to the regions of the silicon dioxide levels not encompassed by the ledges by an amount within a range of from about 10% to about 50%.
4. The integrated structure of claim 1 wherein the regions of the silicon dioxide levels not encompassed by the ledges have thicknesses within a range of from about 20 nm to about 40 nm, and wherein the ledges having thicknesses reduced relative to the regions of the silicon dioxide levels not encompassed by the ledges by an amount within a range of from about 10% to about 50%.
5. The integrated structure of claim 1 wherein the first region of the charge-blocking dielectric is entirely contained within the cavities, and wherein the second region of the charge-blocking dielectric wraps around the ledges as well as extending into the cavities.
6. The integrated structure of claim 5 wherein top and bottom surfaces of the ledges are vertically inset relative to top and bottom surfaces of the regions not encompassed by the ledges by an amount within a range of from about 2 nm to about 7 nm; and wherein the second region of the charge-blocking dielectric has a thickness within a range of from about 2 nm to about 7 nm.
7. The integrated structure of claim 6 wherein the charge-storage structures comprise silicon.
8. The integrated structure of claim 6 wherein L 1 and L 2 differ by less than 5 nm.
9. An integrated structure, comprising:
a stack of alternating silicon dioxide levels and conductive levels;
an opening extending through the stack, the opening having sidewalls along the silicon dioxide levels;
edges of the conductive levels being laterally recessed relative to the sidewalls of the opening to define cavities located between the silicon dioxide levels; the cavities extending from the sidewalls of the opening into the conductive levels;
regions of the silicon dioxide levels over and under the cavities being ledges of the silicon dioxide levels separating adjacent cavities from one another; the ledges being thinned relative to regions of the silicon dioxide levels not encompassed by the ledges, each of the ledges terminating in a La region having a convexly rounded edge along the sidewalls of the opening, the rounded edge extending between an upper surface of the ledge and a bottom surface of the ledge and being convexly curved along its entirety;
charge-blocking dielectric within the cavities;
charge-storage structures within the openings and extending within the cavities, the charge-storage structures having continuous curved outer peripheries;
dielectric material within the openings and extending along the charge-storage structures;
channel material along the dielectric material;
wherein the conductive levels comprise control gates; wherein the charge-blocking dielectric is between the control gates and the charge-storage structures; wherein the charge-storage structures have gate lengths L 1 and the control gates have gate lengths L 2 ; and wherein L 1 and L 2 differ by less than 10 nm; and
wherein the charge-blocking dielectric comprises a first region containing silicon dioxide, a second region containing silicon nitride, and a third region containing oxide; with the second region being between the first and third regions.