Granted Patent B2

US 10,055,285 · App. 14/681,564 · Granted Aug 21, 2018

Abstract

Claims (42)

1. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

communicate with a host based on host logical page size;

error code a portion of a first host logical page of data into a first codeword using a first code rate, wherein the portion of the first host logical page of data comprises less than all bits of the first host logical page of data;

error code a portion of a second host logical page of data into a second codeword using a second code rate, wherein a size of the first codeword is equal to a size of the second codeword, and wherein the portion of the second host logical page of data comprises less than all bits of the second host logical page of data; and

write a quantity of codewords to a physical page of memory, wherein the quantity of codewords correspond to a non-integer quantity of host logical pages of data.

2. The apparatus of claim 1 , wherein the quantity of codewords is constant irrespective of a code rate for any of the quantity of codewords.

3. The apparatus of claim 1 , wherein a payload size of the first codeword is different than a payload size of the second codeword.

4. The apparatus of claim 1 , wherein the controller is configured to receive an input to set a code rate, the code rate comprising a programmable option.

5. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

communicate with a host based on host logical page size;

error code at least a respective portion of each of a plurality of host logical pages of data into a plurality of codewords, wherein the respective portions of each of the plurality of host logical pages of data comprise less than all bits of the plurality of host logical pages of data; and

write the plurality of codewords to one physical page of memory;

wherein a size of the physical page of memory is independent of a size of any of the number of host logical pages of data.

6. The apparatus of claim 5 , wherein the size of the physical page of memory is different than the size of any of the number of host logical pages of data.

7. The apparatus of claim 5 , wherein the controller is further configured to map a location of a starting portion of one of the number of host logical pages of data corresponding to the portion of the number of host logical pages of data error coded as the number of codewords.

8. The apparatus of claim 5 , wherein the controller is configured to error code the portion of the number of host logical pages of data as the number of codewords by error coding the portion of the number of host logical pages of data as the number of codewords each having a payload size equal to a size of each of a number of logical buffer segments.

9. The apparatus of claim 8 , wherein the controller is further configured to buffer payloads of the number of codewords in the number of logical buffer segments prior to writing the number of codewords to the physical page of memory.

10. The apparatus of claim 5 , wherein the controller is configured to error code the portion of the number of host logical pages of data by error coding a particular host logical page of data as a first payload portion of a first codeword and as a second payload portion of a second codeword.

11. The apparatus of claim 10 , wherein a size of the first codeword is equal to a size of the second codeword.

12. A method, comprising:

error coding, via a controller, a portion of a first host logical page of data into a first codeword using a first code rate, wherein the portion of the first host logical page of data comprises less than all bits of the first host logical page of data;

wherein the controller is configured to communicate with a host based on host logical page size, and wherein the controller is coupled to a number of memory devices;

error coding, via the controller, a portion of a second host logical page of data into a second codeword using a second code rate, wherein a size of the first codeword is equal to a size of the second codeword, and wherein the portion of the second host logical page of data comprises less than all bits of the second host logical page of data; and

writing a quantity of codewords to a physical page of memory, wherein the quantity of codewords correspond to a non-integer quantity of host logical pages of data.

13. The method of claim 12 , wherein the quantity of codewords is constant irrespective of a code rate for any of the quantity of codewords.

14. The method of claim 12 , wherein a payload size of the first codeword is different than a payload size of the second codeword.

15. The method of claim 12 , further including receive an input, via the controller, to set a code rate, the code rate comprising a programmable option.

16. A method, comprising:

error coding, via a controller, at least a respective portion of each of a plurality of host logical pages of data into a plurality of codewords, wherein the respective portions of each of the plurality of host logical pages of data comprise less than all bits of the plurality of host logical pages of data;

wherein the controller is configured to communicate with a host based on host logical page size, and wherein the controller is coupled to a number of memory devices; and

writing, via the controller, the plurality of codewords to one physical page of memory;

wherein a size of the physical page of memory is independent of a size of any of the number of host logical pages of data.

17. The method of claim 16 , wherein the size of the physical page of memory is different than the size of any of the number of host logical pages of data.

18. The method of claim 16 , further including mapping, via the controller, a location of a starting portion of one of the number of host logical pages of data corresponding to the portion of the number of host logical pages of data error coded as the number of codewords.

19. The method of claim 16 , wherein error coding the portion of the number of host logical pages of data as the number of codewords comprises error coding the portion of the number of host logical pages of data as the number of codewords each having a payload size equal to a size of each of a number of logical buffer segments.

20. The method of claim 19 , further including buffering payloads of the number of codewords in the number of logical buffer segments prior to writing the number of codewords to the physical page of memory.

21. The method of claim 16 , wherein error coding the portion of the number of host logical pages of data comprises error coding a particular host logical page of data as a first payload portion of a first codeword and as a second payload portion of a second codeword.

22. The method of claim 21 , wherein a size of the first codeword is equal to a size of the second codeword.

Assignments (8)