Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.
1. A semiconductor device comprising:
a plurality of input nodes configured to be supplied with input signals, wherein a number of the input nodes of the plurality of input nodes is equal to M (M is an integer of two or more) to receive M number of the input signals;
a decoder coupled to the plurality of input nodes, the decoder configured to decode the M number of input signals and output N number of decoded signals, wherein N is an integer and is greater than M; and
a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.
2. The semiconductor device according to claim 1 , further comprising:
a plurality of latch circuits having output nodes coupled to the plurality of input nodes, respectively.
3. The semiconductor device according to claim 2 , further comprising:
a plurality of bit lines;
a plurality of word lines; and
a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively;
wherein the fuse circuits are configured to store programmed information that indicates address information of at least a part of one of the plurality of memory cells.
4. The semiconductor device according to claim 3 , wherein the one of the plurality of memory cells is defective.
5. A semiconductor device comprising:
a plurality of input nodes configured to be supplied with input signals, wherein a number of the input nodes of the plurality of input nodes is equal to M (M is an integer of two or more) to receive M number of the input signals;
a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals and the decoder is configured to output 2 M number of the output signals; and
a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.
6. The semiconductor device according to claim 5 , wherein a number of the fuse circuits is equal to 2 M .
7. The semiconductor device according to claim 6 , wherein the decoder is configured to activate one of the decoded signals and inactivate the others of the decoded signals.
8. A semiconductor device comprising:
a plurality of input nodes configured to be supplied with input signals, wherein a number of the input nodes of the plurality of input nodes is equal to M (M is an integer of two or more) to receive M number of the input signals;
a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals and the decoder is configured to output (2 M −1) number of the output signals; and
a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.
9. The semiconductor device according to claim 8 , wherein the decoder is configured to inactivate all of the decoded signals when the input signals take a first pattern and the decoder is configured to activate one of the decoded signals when the input signals take a second pattern different from the first pattern.