Semiconductor memory systems with on-die data buffering
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
1. A memory module comprising:
a substrate;
memory including
a first memory device, the first memory device having a primary interface for carrying out signal transfers with a memory controller via a primary bus, and a secondary interface;
a second memory device, the second memory device including a data interface coupled to the secondary interface;
wherein the memory is coupled to the substrate; and
wherein data transfers between the second memory device and the memory controller are routed through the first memory device.
2. The memory module according to claim 1 , wherein the first memory device is configured as a buffer device, and the second memory device is configured as a memory storage device.
3. The memory module according to claim 1 , wherein the first memory device and the second memory device comprise dynamic random access memory (DRAM) devices.
4. The memory module according to claim 3 , wherein the first memory device is configured as a buffer device, and the second memory device is configured as a memory storage device.
5. The memory module according to claim 4 , wherein the first memory device is stacked with the second memory device in a chip package.
6. The memory module according to claim 5 , further comprising:
plural second memory devices coupled to the first memory device in a multi-drop configuration within the chip package.
7. The memory module according to claim 5 , wherein the memory comprises:
plural first memory devices;
plural second memory devices, at least one second memory device stacked with a first memory device in respective chip packages; and
wherein the memory comprises at least two of the respective chip packages mounted on the substrate.
8. The memory module according to claim 7 , wherein:
the at least two of the respective chip packages are mounted on opposite sides of the substrate.
9. The memory module according to claim 7 , wherein:
the at least two of the respective chip packages are mounted to the substrate in a package-on-package (POP) configuration.
10. A memory module comprising:
a substrate;
memory coupled to the substrate, the memory including a first memory die, wherein the first die includes a mode configuration interface, the mode configuration interface being responsive to
a first mode control signal to configure the first memory die as a buffer device having a primary interface for coupling to a memory controller and a secondary interface for coupling to a second memory die, the buffer device to buffer data transfers between a memory controller and at least one second memory die; and
the mode configuration interface being responsive to a second mode control signal to configure the first memory die as a storage device.
11. The memory module according to claim 10 , wherein the first memory die and the at least one second memory die are stacked in a common package.
12. The memory module according to claim 10 , wherein the first memory die and the at least one second memory die comprise dynamic random access memory (DRAM) devices.
13. The memory module according to claim 10 , wherein the memory includes:
plural first memory devices;
plural second memory devices, at least one second memory device stacked with a first memory device in respective chip packages; and
wherein the memory comprises at least two of the respective chip packages mounted on the substrate.
14. The memory module according to claim 13 , wherein:
the at least two of the respective chip packages are mounted in a package-on-package (POP) configuration.
15. The memory module according to claim 13 , wherein:
the at least two of the respective chip packages are mounted on opposite sides of the substrate.
16. A method of operation in a memory module, the memory module including a substrate, a first memory device and a second memory device coupled to the substrate, the method comprising:
configuring, via a first mode control signal, the first memory device as a buffer device;
configuring, via a second mode control signal, the second memory device as a memory storage device; and
buffering data transfers between the second memory device and a memory controller, the buffering carried out by the first memory device.
17. The method according to claim 16 , wherein the first memory device includes a primary interface and a secondary interface, and wherein the buffering includes:
communicating with a memory controller via the primary interface; and
communicating with the second memory device via the secondary interface.
18. The method according to claim 17 , wherein the buffering further comprises:
communicating with plural second memory devices stacked with the first memory device.
19. The method according to claim 18 , wherein the buffering further comprises:
communicating with the plural second memory devices via a multi-drop bus.
20. The method according to claim 16 , further comprising:
storing data in the second memory device.