IP Library › Granted Patent US 9,871,102
Granted Patent B2
US 9,871,102 · App. 14/684,443 · Granted Jan 16, 2018

Method of forming a single-crystal nanowire finFET

Inventors: Hsin-Yu Chen (Hsinchu County, TW); Huai-Tzu Chiang (Tainan, TW); Sheng-Hao Lin (Hsinchu County, TW); Hao-Ming Lee (Taichung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/0673H01L21/02532H01L21/02667H01L29/0649H01L29/1083H01L29/42392H01L29/66742H01L29/786H01L29/7848
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Quick Facts
Patent No.
US 9,871,102
App. No.
14/684,443
Granted
Jan 16, 2018
Kind
B2
Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

Claims (22)

1. A method of forming a semiconductor device, comprising:

forming two dielectric layers and two first material layers stacked alternately on a substrate;

etching the first material layers and the dielectric layers to expose a portion of the substrate;

forming a second material layer on the portion of the substrate;

transforming the first material layers into two single-crystal material layers; and

completely removing the dielectric layer between the two single-crystal material layers and partially removing the dielectric layer between the single-crystal material layers and the substrate to leave a portion of the dielectric remained on the substrate and not in contact with the two single-crystal material layers, and to form a nanowire structure.

2. The method of forming a semiconductor device according to claim 1 , further comprising:

patterning the first material layers before the transforming of the first material layers.

3. The method of forming a semiconductor device according to claim 1 , further comprising:

patterning the first material layers after the transforming of the first material layers.

4. The method of forming a semiconductor device according to claim 1 , wherein the transforming of the first material layers is performed through a thermal process or a laser irradiation process.

5. The method of forming a semiconductor device according to claim 1 , wherein the second material layer directly contacts the portion of the substrate.

6. The method of forming a semiconductor device according to claim 1 , wherein the portion of the substrate comprises a source/drain region or a supporting region.

7. The method of forming a semiconductor device according to claim 1 , further comprising:

performing an anti-punch through implantation process at the portion of the substrate.

8. The method of forming a semiconductor device according to claim 1 , further comprising:

forming a gate electrode at least partially surrounding the nanowire structure; and

forming a gate dielectric layer between the gate electrode and the nanowire structure.

9. The method of forming a semiconductor device according to claim 8 , wherein before the forming of the gate dielectric layer further comprises:

performing an annealing process to round the nanowire structure.

10. The method of forming a semiconductor device according to claim 1 , wherein the first material layers and the second material layer comprise different materials, or the first material layers and the substrate comprise different materials.

11. The method of forming a semiconductor device according to claim 1 , wherein the second material layer is formed through a low temperature epitaxial process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2015
From: CHEN, HSIN-YU; CHIANG, HUAI-TZU; LIN, SHENG-HAO; LEE, HAO-MING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 035388/0498 →
Priority Claims (1)
CN 2015 1 0111039 · Mar 13, 2015 · national
Continuity (1)
Related Publication 20160268375A1 · Sep 15, 2016