IP Library Granted Patent US 9,244,620
Granted Patent B2
US 9,244,620 · App. 14/684,862 · Granted Jan 26, 2016

Storage device including flash memory and capable of predicting storage device performance based on performance parameters

Inventor: Akihisa Fujimoto (Tokyo, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
G06F3/0613G06F3/061G06F3/0632G06F3/0634G06F3/0679G06F12/0246G06F13/385G11C16/20G06F2206/1014
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Quick Facts
Patent No.
US 9,244,620
App. No.
14/684,862
Granted
Jan 26, 2016
Kind
B2
Abstract

A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Claims (29)

1. A host device which communicates with a storage device, comprising:

a semiconductor memory which has memory areas, a part of the memory areas being assigned to a user area which can be accessed from outside, the user area including allocation units (AUs), each AU including recording units (RUs);

a controller instructing to write data to the semiconductor memory in accordance with a request from the host device;

a register provided in the controller, holding a class value corresponding to a performance class of the storage device and holding information of a size of an AU, the size of the AU being memory management information used to manage the user area, wherein

a worst average write performance of the storage device, which is an average of measured sequential writes performance not including file system information writes, is larger than or equal to performance specified by the class value held in the register,

a write size of each of the sequential writes is a size of one or more of the RUs,

the host device reads the class value from the storage device and requests sequential writes to the storage device while updating file system information in the storage device at an interval of a first period,

the host device comprises a buffer which receives write data for a period at a first rate and outputs data for a second period shorter than the first period at a second rate higher than the first rate, and

the host device controls the first rate or the first period to avoid an overflow of data from the buffer.

2. The device according to claim 1 , wherein

the host device updates the file system information for a third period, which is equal to the first period minus the second period.

3. The device according to claim 1 , wherein

the host device updates the file system information at an interval of the first period.

4. The device according to claim 1 , wherein

the host device is able to access the register.

5. A host device which communicates with a storage device, comprising:

a semiconductor memory which has memory areas, a part of the memory areas being assigned to a user area which can be accessed from outside, the user area including allocation units (AUs), each AU including recording units (RUs);

a controller instructing to write data to the semiconductor memory in accordance with a request from the host device;

a register provided in the controller, holding a class value corresponding to a performance class of the storage device and holding information of a size of an AU, the size of the AU being memory management information used to manage the user area, wherein

a worst average write performance of the storage device, which is an average of measured sequential writes performance not including file system information writes, is larger than or equal to performance specified by the class value held in the register,

a write size of each of the sequential writes is a size of one or more of the RUs,

the host device reads the class value from the storage device and requests sequential writes to the storage device while updating file system information in the storage device at an interval of a first period, and

the host device controls a first rate requested from an application in the hot device or the first period to allow the storage device to write data received from the host device with the performance specified by the class value within a second period shorter than the first period.

6. The device according to claim 5 , wherein

the host device updates the file system information for a third period, which is equal to the first period minus the second period.

7. The device according to claim 5 , wherein

the host device updates the file system information at an interval of the first period.

8. The device according to claim 5 , wherein

the host device is able to access the register.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
Priority Claims (2)
JP 2004-204028 · Jul 12, 2004 · national
JP 2004-342275 · Nov 26, 2004 · national
Continuity (6)
Continuation 14445374 · Jul 29, 2014
Continuation 13962455 · Aug 8, 2013
Continuation 13096731 · Apr 28, 2011
Division 11557120 · Nov 7, 2006
Continuation PCTJP2005013104 · Jul 8, 2005
Related Publication 20150242135A1 · Aug 27, 2015