Electrostatic discharge (ESD) silicon controlled rectifier (SCR) with lateral gated section
In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.
1. An electrostatic discharge (ESD) protection circuit comprising:
a shallow trench isolation (STI)-bound silicon controlled rectifier (SCR) coupled between an input/output conductor and a voltage rail, wherein the STI-bound SCR extends between a first semiconductor region and a second semiconductor region, wherein the first semiconductor region and the second semiconductor region are separated by an STI region; and
a gated SCR coupled between the input/output conductor and the voltage rail.
2. The ESD protection circuit as recited in claim 1 wherein the STI-bound SCR and the gated SCR are formed on a semiconductor substrate, and wherein the STI-bound SCR is formed to be perpendicular to the gated SCR in a layout view of the semiconductor substrate.
3. The ESD protection circuit as recited in claim 2 wherein the STI-bound SCR is formed between two adjacent regions of fins in the semiconductor substrate.
4. The ESD protection circuit as recited in claim 3 wherein the gated SCR is formed within one of the two adjacent regions of fins.
5. The ESD protection circuit as recited in claim 2 wherein a first node of the STI-bound SCR and a second node of the gated SCR are in a same diffusion area in the semiconductor substrate.
6. The ESD protection circuit as recited in claim 2 wherein a first node of the STI-bound SCR and a second node of the gated SCR are in a same N-well in the semiconductor substrate.
7. The ESD protection circuit as recited in claim 2 further comprising a trigger diode configured to trigger the STI-bound SCR and the gated SCR.
8. The ESD protection circuit as recited in claim 7 wherein the trigger diode is in a same region of fins as the STI-bound SCR and the gated SCR.
9. The ESD protection circuit as recited in claim 1 comprising:
an N-type (N)-well formed in a semiconductor substrate wherein an area around the N-well is a P-well forming a first PN junction;
a P-type highly doped (P+) area formed in the N-well, forming a second PN junction;
a first N-type highly doped (N+) area formed in the P-well, forming a third PN junction, wherein the first PN junction, the second PN junction, and the third PN junction form the STI-bound SCR; and
a second N+ region formed in the P-well forming a fourth PN junction, wherein the first PN junction, the second PN junction, and the fourth PN junction forming the gated SCR.
10. The ESD protection circuit as recited in claim 1 wherein the voltage rail is a ground rail.
11. A fin field effect transistor (FinFET) electrostatic discharge (ESD) protection circuit comprising:
an N-type (N)-well formed in a semiconductor substrate wherein an area around the N-well is a P-well forming a first PN junction;
a P-type highly doped (P+) area formed in the N-well, forming a second PN junction;
a first N-type highly doped (N+) area formed in the P-well, forming a third PN junction, wherein the first PN junction, the second PN junction, and the third PN junction form a first silicon controlled rectifier (SCR); and
a second N+ region formed in the P-well forming a fourth PN junction, wherein the first PN junction, the second PN junction, and the fourth PN junction forming a second SCR that is perpendicular to the first SCR.
12. The FinFET ESD protection circuit as recited in claim 11 wherein the first SCR is a shallow trench isolation (STI)-bound SCR.
13. The FinFET ESD protection circuit as recited in claim 11 wherein the second SCR is a gated SCR.
14. The FinFET ESD protection circuit as recited in claim 11 wherein the first and second N+ regions are coupled to a ground input, and wherein the first and second SCRs are electrically coupled in parallel.
15. The FinFET ESD protection circuit as recited in claim 11 further comprising a second N-well having N+ and P+ regions, wherein a diode in the second N-well is a trigger for the first SCR and the second SCR.
16. A fin field effect transistor (FinFET) electrostatic discharge (ESD) protection circuit comprising:
a first region of fins and a second region of fins on a semiconductor substrate, wherein the first and second regions of fins are separated by an isolation structure;
a first silicon controlled rectifier (SCR) formed between the first region of fins and the second region of fins; and
a second SCR formed within the first region of fins and perpendicular to the first SCR, wherein the first and second SCR share a node within the first region of fins.
17. The FinFET ESD protection circuit as recited in claim 16 wherein the isolation structure comprises a shallow trench isolation (STI) structure.
18. The FinFET ESD protection circuit as recited in claim 16 wherein the first SCR is a shallow trench isolation (STI)-bound SCR.
19. The FinFET ESD protection circuit as recited in claim 18 wherein the second SCR is a gated SCR.
20. The FinFET ESD protection circuit as recited in claim 16 wherein the second SCR is covered by a gate material.