Power Semiconductor Device with Low RDSON and High Breakdown Voltage
A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench.
1 . A semiconductor structure comprising:
a trench having substantially parallel trench sidewalls;
a tapered dielectric liner in said trench, said tapered dielectric liner having slanted dielectric sidewalls;
a conductive filler enclosed by said slanted dielectric sidewalls.
2 . The semiconductor structure of claim 1 , wherein said conductive filler is a field plate in a power transistor.
3 . The semiconductor structure of claim 1 , wherein said trench is situated in a drift region of a power transistor.
4 . The structure of claim 1 , wherein said tapered dielectric liner comprises silicon oxide.
5 . The structure of claim 1 , wherein said conductive filler comprises polysilicon.
6 . The semiconductor structure of claim 1 , wherein said semiconductor structure is part of a power transistor.
7 . The semiconductor structure of claim 6 , wherein said power transistor in a vertical conduction semiconductor device.
8 . A method comprising:
forming a trench in a semiconductor structure;
forming a dielectric liner in said trench;
forming a sacrificial material covering said dielectric liner;
etching said sacrificial material with an etchant at a first etch rate while etching said dielectric liner with said etchant at a second etch rate, thereby producing a tapered dielectric liner having slanted dielectric sidewalls.
9 . The method of claim 8 , further comprising depositing a conductive filler in said trench, said conductive filler being enclosed by said slanted dielectric sidewalls.
10 . The method of claim 8 , wherein said first etch rate is greater than said second etch rate.
11 . The method of claim 8 , wherein said slanted dielectric sidewalls have a substantially constant slope.
12 . The method of claim 8 , wherein said etching said dielectric liner with said etchant at said second etch rate comprises an isotropic etching of said sacrificial material.
13 . The method of claim 8 , wherein said sacrificial material comprises an organic material.
14 . The method of claim 8 , wherein said dielectric liner comprises silicon oxide.
15 . The method of claim 9 , wherein said conductive filler comprises polysilicon.
16 . A method comprising:
forming a trench in a semiconductor structure;
forming a dielectric liner in said trench;
forming a sacrificial material covering said dielectric liner;
etching, with a first etchant, said sacrificial material and said dielectric liner;
etching, with a second etchant, said sacrificial material and said dielectric liner, thereby producing a tapered dielectric liner having slanted dielectric sidewalls.
17 . The method of claim 16 , wherein said dielectric liner comprises silicon oxide.
18 . The method of claim 16 , wherein said etching with said second etchant comprises an isotropic etching of said dielectric liner.
19 . The method of claim 16 , wherein said etching with said first etchant is performed without substantially etching said dielectric liner.
20 . The method of claim 16 , wherein said etching with said second etchant is performed without substantially etching said sacrificial material.