Error control in memory storage systems
View Patent ↗A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
1. A method, comprising:
reading, via a processor, a codeword from a memory based on a reference level;
determining, via a controller, a syndrome of the codeword;
determining, via the controller, whether the codeword contains an error based, at least in part, on the syndrome;
based on the presence of an error, reading, via the processor, binary values from memory locations surrounding the codeword; and
calculating, via the controller, a new reference level for reading the codeword, the new reference level corresponding to the binary values from the memory locations surrounding the codeword, wherein calculating the new reference level comprises:
determining a percentage of the memory locations surrounding the codeword storing a high voltage level,
calculating the new reference voltage corresponding to the binary values of the codeword based on the percentage of the memory locations surrounding the codeword storing the high voltage level, wherein the new reference level responsive to a large percentage of the memory cells storing the high voltage level is greater than the new reference level responsive to a small percentage of the memory cells storing the high voltage level.
2. The method of claim 1 , further comprising:
reading the codeword from the memory based on the new reference level;
determining the syndrome of the codeword; and
determining whether the codeword read from the memory based on the new reference level contains an error based, at least in part, on the syndrome.
3. The method of claim 1 , wherein the new reference level is a higher voltage reference.
4. The method of claim 1 , wherein reading a codeword from a memory based on a reference level comprises determining a value for each binary digit of the codeword based on the reference level.
5. The method of claim 4 , wherein determining a value for each binary digit of the codeword based on the reference level comprises determining the value for each binary digit of the codeword based on two or more reference levels.
6. The method of claim 1 , wherein a pattern of the contents from memory locations surrounding the codeword affects a gate voltage of each binary digit of the codeword.
7. A method, comprising:
determining, with a logic module of a microcontroller, a pattern of memory cells surrounding a codeword; and
determining, with the logic module, an increase in voltage corresponding to binary values of the codeword based on the pattern, wherein determining the increase in the voltage comprises:
loading the pattern of memory cells surrounding the codeword into reference selector logic of a memory,
determining a percentage of the memory cells surrounding the codeword storing a high voltage level, and
calculating the increase in the voltage corresponding to the binary values of the codeword based on the percentage of the memory cells surrounding the codeword storing the high voltage level, wherein the increase in the voltage corresponding to the binary values of the codeword increases a first reference level for reading the codeword.
8. The method of claim 7 , further comprising:
determining, with the logic module, the first reference level for the codeword;
reading the codeword from a memory location at a second reference level; and
determining a syndrome of the codeword.
9. The method of claim 8 , wherein the second reference level is lower than the first reference level.
10. The method of claim 7 , further comprising reading the memory cells surrounding the codeword.
11. The method of claim 7 , wherein the codeword is associated with a portion of a data word striped across a plurality of memories.
12. The method of claim 7 , further comprising:
determining a syndrome of the codeword based on the first reference level; and
based on the syndrome being zero, refreshing the codeword.
13. An apparatus, comprising:
a memory array configured to store a portion of a data word and an associated codeword; and
a controller coupled to the memory array and configured to determine values stored in memory cells surrounding the codeword, and further configured to determine if a reference level associated with the codeword is affected by the values stored in the memory cells surrounding the codeword.
14. The apparatus of claim 13 , wherein the controller is configured to determine a percentage of the memory cells surrounding the codeword having a high logic level stored therein, the controller is further configured to increase the reference level associated with the codeword based on the percentage.
15. The apparatus of claim 14 , further including sense circuitry coupled to the plurality of memory devices and configured to read the codeword at an increased reference level, and wherein the controller is configured to determine a syndrome of the codeword read at the increased reference level.
16. The apparatus of claim 13 , wherein the controller is configured to determine a syndrome of the codeword read at the reference level.
17. The apparatus of claim 16 , wherein the controller is configured to calculate a new reference level for the codeword based on the syndrome indicating an error in the codeword.
18. The apparatus of claim 13 , wherein the controller is configured to autonomously determine if a reference level associated with the codeword is affected by the values stored in the memory cells surrounding the codeword, and further to determine a new reference level for the codeword.