IP Library › Granted Patent US 9,479,366
Granted Patent B2
US 9,479,366 · App. 14/686,343 · Granted Oct 25, 2016

IIR DFE updating gain and time constants using LMS equations

Inventors: Kevin Zheng (Alhambra, CA); Reza Hoshyar (San Jose, CA); Nirmal Warke (Saratoga, CA); Ali Kiaei (San Jose, CA); Ahmad Bahai (Lafayette, CA)
Assignee: Texas Instruments Incorporated
H04L25/03267H04L25/03019H04L25/03057H04L25/03261H04L2025/0349H04L2025/03636
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,479,366
App. No.
14/686,343
Granted
Oct 25, 2016
Kind
B2
Abstract

A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The method includes, for a given IIR path for a received signal, updating gain of the given IIR path using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation; and updating a time constant of the given IIR path using a respective monitor tap error-data correlation with a second LMS update equation.

Claims (25)

1. A Decision Feedback Equalizer (DFE) comprising:

a set of data slicers connected to provide a signal to a data delay line having a plurality of digital delay blocks, the set of data slicers further connected to receive an input signal that has been provided through an adder; and

a first Infinite Impulse Response (IIR) tap for a first IIR path, the first IIR tap comprising a first digital-to-analog converter (DAC) and a first filter, the first IIR tap being connected to receive a signal output from a respective digital delay block that has been selected for a pivot tap for the first IIR path and further being connected to provide a correction signal to the adder;

in which coefficients for the first DAC are connected to be updated using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation and coefficients for the first filter are connected to be updated using a respective error-data correlation for a monitor tap for the first IIR path with a second LMS update equation; and

at least one additional IIR tap for a respective IIR path, each additional IIR tap including:

a respective DAC and a respective filter;

each additional IIR tap being connected to receive the signal from a respective digital delay block that has been selected for a pivot tap for the additional IIR path and to provide a respective correction signal to the adder;

in which coefficients for the respective DAC are connected to be updated using another respective pivot tap error-data correlation with the first Least Mean Square (LMS) update equation; and

coefficients for the respective filter are updated using another respective error-data correlation for a monitor tap for the additional IIR path with the second LMS update equation.

2. The DFE as recited in claim 1 in which adaptation of the first IIR path is performed alternately with adaptation of the at least one additional IIR path every adaptation period.

3. The DFE as recited in claim 2 wherein the adaptation period is increased in length once steady state operation is achieved.

4. The DFE as recited in claim 3 wherein the adaptation of the first IIR path and the at least one additional IIR paths starts with an IIR path having a longest time constant and successively adapts IIR paths having a next longest time constant.

5. The DFE as recited in claim 3 wherein the adaptation of the first IIR path and the at least one additional IIR paths starts with an IIR path having a shortest time constant and successively adapts IIR paths having a next shortest time constant.

6. The DFE as recited in claim 3 further comprising one or more Finite Impulse Response (FIR) taps each comprising a respective DAC and being connected to receive the signal from a respective digital delay block that has been selected for a FIR tap and further being connected to provide a correction signal to the adder.

7. A receiver for a high-speed signal, comprising:

a Continuous Time Linear Equalizer connected to receive the high-speed signal, to cancel Inter-Signal Interference (ISI) and provide a partially equalized signal; and

a Decision Feedback Equalizer (DFE) connected to receive the partially equalized signal and to provide an output signal containing recognized symbols, the DFE comprising

a set of data slicers connected to provide a signal to a data delay line having a plurality of digital delay blocks, the set of data slicers further connected to receive an input signal that has been provided through an adder; and

a first Infinite Impulse Response (IIR) tap for a first IIR path, the first IIR tap comprising a first digital-to-analog converter (DAC) and a first filter, the first IIR tap being connected to receive a signal from a respective digital delay block that has been selected for a pivot tap for the first IIR path and further being connected to provide a correction signal to the adder;

in which coefficients for the first DAC are connected to be updated using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation and coefficients for the first filter are connected to be updated using a respective error-data correlation for a monitor tap for the first IIR path with a second LMS update equation; and

at least one additional IIR tap for a respective IIR path, each additional IIR tap including a respective DAC and a respective filter;

each additional IIR tap being connected to receive the signal from a respective digital delay block that has been selected for a pivot tap for the respective IIR path and to provide a respective correction signal to the adder;

in which coefficients for the respective DAC are connected to be updated using another respective pivot tap error-data correlation with the first Least Mean Square (LMS) update equation; and

coefficients for the respective filter are updated using another respective error-data correlation for a monitor tap for the respective IIR path with the second LMS update equation.

8. The receiver for the high-speed signal as recited in claim 7 in which adaptation of the first IIR path is performed alternately with adaptation of the at least one additional IIR path every adaptation period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2015
From: ZHENG, KEVIN; HOSHYAR, REZA; WARKE, NIRMAL; KIAEI, ALI; BAHAI, AHMAD
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 035415/0926 →
Continuity (3)
Provisional Application 62108790 · Jan 28, 2015
Provisional Application 62108796 · Jan 28, 2015
Related Publication 20160218889A1 · Jul 28, 2016