IP Library Granted Patent US 10,078,604
Granted Patent B1
US 10,078,604 · App. 14/690,349 · Granted Sep 18, 2018

Interrupt coalescing

Inventors: Arnaldo Cristobal (Bocaue, PH); Marlon Verdan (Paranaque, PH)
Assignee: BiTMICRO Networks, Inc.
G06F13/24G06F9/4825
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,078,604
App. No.
14/690,349
Granted
Sep 18, 2018
Kind
B1
Abstract

In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.

Claims (45)

1. A method, comprising:

collecting a plurality of interrupts;

if coalesced active interrupts have not exceeded an interrupt count limit, then enabling a timer; and

servicing the coalesced active interrupts to a processor if the coalesced active interrupts have exceeded the interrupt count limit or if a timeout count of the timer has expired;

wherein servicing the coalesced active interrupts comprises:

comparing a sum of active interrupts to a minimum count range 0 and up to a minimum count range K, wherein K is an integer;

if the sum of the active interrupts is equal to or is greater than the minimum count range 0, and if the sum of the active interrupts is less than the minimum count range K, then waiting for the timeout count to expire before servicing the coalesced active interrupts.

2. The method of claim 1 , wherein servicing the coalesced active interrupts comprises:

if a sum of active interrupts is equal to or greater than the interrupt count limit or is less than a predetermined value set on a minimum count range 0, then servicing the coalesced active interrupts.

3. The method of claim 1 , wherein servicing the coalesced active interrupts comprises:

comparing a sum of active interrupts to first predetermined value set on a minimum count range 0;

if the sum of the active interrupts is less than the minimum count range 0, then servicing the coalesced active interrupts.

4. The method of claim 1 , wherein servicing the coalesced active interrupts comprises:

comparing a sum of active interrupts to a maximum threshold count;

if the sum of the active interrupts is equal to or greater than the maximum threshold count, then servicing the coalesced active interrupts.

5. The method of claim 1 , further comprising:

asserting a coalesced interrupt signal to permit servicing of the coalesced active interrupts.

6. The method of claim 5 , further comprising:

clearing an interrupt stack register so that the coalesced interrupt signal is de-asserted.

7. The method of claim 1 , wherein the interrupt count limit and timeout count are programmable values.

8. An apparatus, comprising:

an interrupt controller configured to collect a plurality of interrupts, configured to enable a timer if coalesced active interrupts have not exceeded an interrupt count limit, and configured to service the coalesced active interrupts to a processor if the coalesced active interrupts have exceeded the interrupt count limit or if a timeout count of the timer has expired;

wherein the interrupt controller is configured to wait for the timeout count to expire before servicing the coalesced active interrupts based on a comparison of a sum of active interrupts to a minimum count range 0 and up to a minimum count range K, wherein K is an integer and if the sum of the active interrupts is equal to or is greater than the minimum count range 0, and if the sum of the active interrupts is less than the minimum count range K.

9. The apparatus of claim 8 , wherein the interrupt controller is configured to service the coalesced active interrupts if a sum of active interrupts is equal to or greater than the interrupt count limit or is less than a predetermined value set on a minimum count range 0.

10. The apparatus of claim 8 , wherein the interrupt controller is configured to service the coalesced active interrupts based on a comparison of a sum of active interrupts to first predetermined value set on a minimum count range 0 and if the sum of the active interrupts is less than the minimum count range 0.

11. The apparatus of claim 8 , wherein the interrupt controller is configured to service the coalesced active interrupts based on a comparison of a sum of active interrupts to a maximum threshold count and if the sum of the active interrupts is equal to or greater than the maximum threshold count.

12. The apparatus of claim 8 , wherein the interrupt controller is configured to assert a coalesced interrupt signal to permit servicing of the coalesced active interrupts.

13. The apparatus of claim 12 , wherein the interrupt controller is configured to clear an interrupt stack register so that the coalesced interrupt signal is de-asserted.

14. The apparatus of claim 8 , wherein the interrupt count limit and timeout count are programmable values.

15. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to:

collect a plurality of interrupts;

enable a timer if coalesced active interrupts have not exceeded an interrupt count limit; and

service the coalesced active interrupts to a processor if the coalesced active interrupts have exceeded the interrupt count limit or if a timeout count of the timer has expired;

wherein the instructions are operable to permit the apparatus to service the coalesced active interrupts so that the apparatus:

compares a sum of active interrupts to a minimum count range 0 and up to a minimum count range K, wherein K is an integer;

if the sum of the active interrupts is equal to or is greater than the minimum count range 0, and if the sum of the active interrupts is less than the minimum count range K, then the apparatus waits for the timeout count to expire before servicing the coalesced active interrupts.

16. The article of manufacture of claim 15 , wherein the instructions are operable to permit the apparatus to service the coalesced active interrupts so that

if a sum of active interrupts is equal to or greater than the interrupt count limit or is less than a predetermined value set on a minimum count range 0, then the apparatus services the coalesced active interrupts.

17. The article of manufacture of claim 15 , wherein the instructions are operable to permit the apparatus to service the coalesced active interrupts so that the apparatus

compares a sum of active interrupts to first predetermined value set on a minimum count range 0; and

if the sum of the active interrupts is less than the minimum count range 0, then the apparatus services the coalesced active interrupts.

18. The article of manufacture of claim 15 , wherein the instructions are operable to permit the apparatus to service the coalesced active interrupts wherein the apparatus

compares a sum of active interrupts to a maximum threshold count; and

if the sum of the active interrupts is equal to or greater than the maximum threshold count, then the apparatus services the coalesced active interrupts.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2021
From: BITMICRO NETWORKS, INC.
To: BITMICRO LLC
Reel/Frame 055840/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2018
From: CRISTOBAL, ARNALDO; VERDAN, MARLON
To: BITMICRO NETWORKS, INC.
Reel/Frame 046531/0349 →
Continuity (1)
Provisional Application 61980632 · Apr 17, 2014
Cited By (1)
US 12,737,027