Low power and compact area digital integrator for a digital phase detector

1. A circuit comprising:

a first circuit configured to receive a reference signal and a source signal and to generate a correction signal indicating a difference in phase between the reference signal and the source signal;

a second circuit configured to receive the correction signal and to generate a digital signal indicating a phase-to-digital conversion of the correction signal;

a third circuit configured to receive the digital signal and to generate a control signal indicating a converted value of the digital signal;

a fourth circuit configured to receive the control signal and to generate a source signal in response to the control signal; and

a fifth circuit configured to compare a characteristic of the digital signal to a predetermined range and to generate a lock signal if a characteristic of the digital signal indicates the ability to achieve phase-lock.

2. The circuit of claim 1 , wherein the predetermined range is temperature-compensated according to a temperature of the circuit.

3. The circuit of claim 2 , wherein the fifth circuit is configured to permit the temperature compensation of the predetermined range to be changed.

4. The circuit of claim 1 , wherein the predetermined range is temperature-compensated according to a temperature of the fourth circuit.

5. The circuit of claim 4 , wherein the fifth circuit is configured to permit the temperature compensation of the predetermined range to be changed according to a temperature dependency of the fourth circuit.

6. The circuit of claim 1 , wherein the fifth circuit is configured to permit temperature compensation in the digital domain.

7. The circuit of claim 1 , wherein the predetermined range is associated with a range of voltages achievable by the circuit.

8. The circuit of claim 7 , wherein the predetermined range includes a low threshold associated with a minimum voltage achievable by the circuit and a high threshold associated with a maximum voltage achievable by the circuit.

9. The circuit of claim 1 , wherein the predetermined range is associated with a range of voltages that the circuit is capable of delivering to the fourth circuit.

10. The circuit of claim 9 , wherein the predetermined range includes a low threshold associated with a minimum voltage that the circuit is capable of delivering to the fourth circuit and a high threshold associated with a maximum voltage that the circuit is capable of delivering to the fourth circuit.

11. The circuit of claim 1 , wherein the second circuit is further configured to decimate the digital signal.

12. The circuit of claim 1 , wherein the second circuit is further configured to down-sample the digital signal.

13. The circuit of claim 1 , wherein the second circuit is further configured to decimate and down-sample the digital signal.

14. The circuit of claim 1 , wherein the second circuit includes a continuous-time sigma-delta modulator.

15. The circuit of claim 1 , wherein:

the third circuit includes an accumulator and a digital-to-analog converter, and

the control signal includes a converted voltage of a digital word generated by the accumulator from the digital signal.

16. The circuit of claim 1 , wherein the first circuitry includes a phase detector configured to generate the correction signal.

17. The circuit of claim 1 , wherein:

the third circuitry includes an accumulator,

the control signal includes a digital word generated by the accumulator from the digital signal, and

the fourth circuitry includes a digitally-controlled oscillator configured to generate the source signal in response to the digital word.

18. The circuit of claim 17 , wherein the accumulator includes a counter.

19. The circuit of claim 17 , wherein the accumulator includes one or more of:

an 11-bit up-down counter,

a 12-bit up-down counter, and

an 18-bit up-down counter.

20. The circuit of claim 1 , wherein the fourth circuitry includes a voltage-controlled oscillator.