Thin film RDL for nanochip package
View Patent ↗A high density film adapted for nanochip package comprises three redistribution layers. A bottom redistribution circuit has a plurality of first bottom pads adapted for a nanochip to mount; and has a plurality of first top pads. The density of the first bottom pads is higher than the density of the first top pads. A middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads. The density of the second bottom pads is higher than the density of the second top pads. A top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads; and has a plurality of third top pads. The density of the third bottom pads is higher than the density of the third top pads.
1. A thin film RDL for nanochip package, comprising:
a bottom redistribution circuit, having a plurality of first bottom pads adapted for at least one nanochip to mount; and having a plurality of first top pads; wherein a density of the first bottom pads is higher than a density of the first top pads;
a middle redistribution circuit formed on top of the bottom redistribution circuit, having a plurality of second bottom pads electrically coupled to the first top pads, and having a plurality of second top pads; wherein a density of the second bottom pads is higher than a density of the second top pads; and
a top redistribution circuit formed on top of the middle redistribution circuit, having a plurality of third bottom pads electrically coupled to the second top pads, and having a plurality of third top pads; wherein a density of the third bottom pads is higher than a density of the third top pads.
2. A thin film RDL for nanochip package as claimed in claim 1 , further comprising:
at least a nanochip, electrically coupled to the first bottom pads.
3. A thin film RDL for nanochip package as claimed in claim 1 , wherein
the bottom redistribution circuit is fabricated following design rules of around 0.1 um;
the middle redistribution circuit is fabricated following design rules of around 1 um; and
the bottom redistribution circuit is fabricated following design rules of around 10 um.
4. A thin film RDL for nanochip package as claimed in claim 1 , wherein
the density of the first bottom pads is around ten times the density of the first top pads;
the density of the second bottom pads is around ten times the density of the second top pads; and
the density of the third bottom pads is around ten times the density of the third top pads.
5. A thin film RDL for nanochip package as claimed in claim 1 , further comprises
a plurality of dielectric layers, each embeds one of the redistribution circuits; and
a fiber-based filler is filled in at least one of the dielectric layers.
6. A process for fabricating a nanochip package, comprising:
forming a bottom redistribution circuit; the bottom redistribution circuit has a plurality of first bottom pads adapted for at least one nanochip to mount; and has a plurality of first top pads; wherein a density of the first bottom pads is higher than a density of the first top pads;
forming a middle redistribution circuit on top of the bottom redistribution circuit; the middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads; wherein a density of the second bottom pads is higher than a density of the second top pads; and
forming a top redistribution circuit on top of the middle redistribution circuit; the top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads, and has a plurality of third top pads; wherein a density of the third bottom pads is higher than a density of the third top pads.
7. A process for fabricating a nanochip package as claimed in claim 6 , further comprising:
preparing at least a nanochip; and
coupling the nanochip onto the first bottom pads.
8. A process for fabricating a nanochip package as claimed in claim 6 , wherein
the bottom redistribution circuit is fabricated following design rules of around 0.1 um;
the middle redistribution circuit is fabricated following design rules of around 1 um; and
the bottom redistribution circuit is fabricated following design rules of around 10 um.
9. A process for fabricating a nanochip package as claimed in claim 6 , wherein
the density of the first bottom pads is around ten times the density of the first top pads;
the density of the second bottom pads is around ten times the density of the second top pads; and
the density of the third bottom pads is around ten times the density of the third top pads.
10. A process for fabricating a nanochip package as claimed in claim 6 , wherein the RDL comprising:
a first dielectric layer embeds the first redistribution circuit;
a second dielectric layer embeds the second redistribution circuit;
a third dielectric layer embeds the third redistribution circuit; and
a fiber-based filler is filled in at least one of the dielectric layers.