IP Library Granted Patent US 9,312,836
Granted Patent B1
US 9,312,836 · App. 14/701,480 · Granted Apr 12, 2016

Reduced pin full feature load switch

Inventors: John Othniel McDonald (Mountain House, CA); Jie Chen (Saratoga, CA); Chen-Yu Wang (San Jose, CA)
Assignee: Silego Technology, Inc.
H03K5/12H03K4/00H03K4/085H03K4/48
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Quick Facts
Patent No.
US 9,312,836
App. No.
14/701,480
Granted
Apr 12, 2016
Kind
B1
Abstract

A four pin integrated circuit MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) load switch is disclosed that provides full features including adjustable ramp time/rate, adjustable discharge time/rate, temperature control, over-current control, and short circuit protection. In some embodiments, the adjustable ramp is based on the voltage or current input into the integrated circuit.

Claims (34)

1. An integrated circuit, comprising:

a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) configured as a switch; and

circuitry for providing an adjustable ramp rate for MOSFET turn-on, wherein a value of the ramp rate depends on a current on an input pin of the integrated circuit;

wherein the integrated circuit comprises only four pins including the input pin, a drain pin, a source pin, and a ground pin.

2. The integrated circuit of claim 1 , wherein the switch comprises a load switch.

3. The integrated circuit of claim 1 , wherein the switch comprises a high-side load switch.

4. The integrated circuit of claim 1 , wherein the adjustable ramp rate is linear and closed loop.

5. The integrated circuit of claim 1 , wherein the current on the input pin of the integrated circuit is set by an external resistor.

6. The integrated circuit of claim 1 , wherein the input pin of the integrated circuit is held at a constant reference voltage.

7. The integrated circuit of claim 1 , wherein the value of the ramp rate is proportional to the current on the input pin.

8. The integrated circuit of claim 1 , wherein the circuitry for providing an adjustable ramp rate comprises an amplifier.

9. The integrated circuit of claim 1 , wherein the circuitry for providing an adjustable ramp rate comprises a digital buffer.

10. The integrated circuit of claim 1 , wherein the circuitry for providing an adjustable ramp rate is configured to translate current input into the integrated circuit into a linear, closed loop ramp.

11. The integrated circuit of claim 1 , wherein an adjustable discharge is provided via an external discharge resistor placed in series with the ground pin of the integrated circuit.

12. The integrated circuit of claim 1 , further comprising circuitry for over-temperature protection.

13. The integrated circuit of claim 1 , further comprising circuitry for over-current protection.

14. The integrated circuit of claim 1 , further comprising circuitry for short circuit protection.

15. A method, comprising:

configuring a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a switch; and

configuring circuitry for providing an adjustable ramp rate for MOSFET turn-on;

wherein the MOSFET and the circuitry form a four pin integrated circuit comprising an input pin, a drain pin, a source pin, and a ground pin and wherein a value of the ramp rate depends on a current on the input pin of the integrated circuit.

16. The method of claim 15 , wherein the current on the input pin of the integrated circuit is set by an external resistor.

17. The method of claim 15 , wherein the value of the ramp rate is proportional to the current on the input pin.

18. The method of claim 15 , further comprising configuring circuitry for over-temperature protection.

19. The method of claim 15 , further comprising configuring circuitry for over-current protection.

20. The method of claim 15 , further comprising configuring circuitry for short circuit protection.

21. The method of claim 15 , wherein the switch comprises a load switch.

22. The method of claim 15 , wherein the switch comprises a high-side load switch.

23. The method of claim 15 , wherein the adjustable ramp rate is linear and closed loop.

24. The method of claim 15 , wherein the input pin of the integrated circuit is held at a constant reference voltage.

25. The method of claim 15 , wherein the circuitry for providing an adjustable ramp rate comprises an amplifier.

26. The method of claim 15 , wherein the circuitry for providing an adjustable ramp rate comprises a digital buffer.

27. The method of claim 15 , wherein the circuitry for providing an adjustable ramp rate is configured to translate current input into the integrated circuit into a linear, closed loop ramp.

28. The method of claim 15 , wherein an adjustable discharge is provided via an external discharge resistor placed in series with the ground pin of the integrated circuit.

Assignments (1)
CHANGE OF NAME Recorded Nov 22, 2022
From: SILEGO TECHNOLOGY, INC.
To: RENESAS DESIGN TECHNOLOGY INC.
Reel/Frame 061987/0827 →
Continuity (3)
Continuation 13922121 · Jun 19, 2013
Provisional Application 61661749 · Jun 19, 2012
Provisional Application 61699749 · Sep 11, 2012