Management of shared pipeline resource usage based on level information

1. A method for adapting application processing based on level information of a cache memory system, the method comprising:

requesting, by a core from the cache memory system, a data block,

the cache memory system including a plurality of cache levels and a plurality of ways;

extracting by the cache memory system, from information stored in the cache memory system, a cache level and way in which the requested data block resides, from among the plurality of cache levels and the plurality of ways of the cache memory system; and

after the extracting,

informing the core of the extracted cache level of the cache memory system;

predicting, by the core, a latency associated with retrieving the requested data block based on the extracted cache level; and

adapting, by the core, an allocation of shared pipeline resources associated with a pipeline which is processing an application based on the predicted latency.

2. The method of claim 1 , wherein the steps of extracting the cache level and informing the core further comprises the steps of:

issuing a memory request for the data block;

then, finding an entry in a location buffer associated with the data block requested by the memory request;

finding, within the entry, level information associated with the data block; and

sending the level information associated with the data block to the core.

3. The method of claim 2 , further comprising determining whether a memory instruction associated with requesting the data block is a slow memory instruction based on whether the extracted cache level of the cache memory system indicates a latency associated with providing the data block to the core which is greater than a predetermined threshold.

4. The method of claim 3 , wherein the step of adapting further comprises releasing already allocated pipeline resources allocated to the memory instruction, or instructions dependent on the memory instruction, if the memory instruction is determined to be a slow memory instruction.

5. The method of claim 3 , wherein the pipeline is capable of simultaneously executing instructions from at least two threads, wherein the step of adapting further comprises reprioritizing execution of threads in the pipeline associated with the application when a slow memory instruction is identified.

6. The method of claim 5 , wherein the reprioritization involves halting at least one of the threads for a period of time.

7. The method of claim 6 , wherein the period of time is determined by one or more memory system levels of one or more outstanding requests for data blocks.

8. The method of claim 2 , wherein the step of adapting further comprises delaying allocation of pipeline resources for a period which is based on a latency associated with the level information associated with the data block.

9. The method of claim 8 , wherein the pipeline resources are physical registers or space in an issue queue.

10. The method of claim 2 , wherein the pipeline is capable of simultaneously executing instructions from at least two threads, wherein the step of adapting further comprises adjusting a priority of a thread that is in the pipeline and being executed by the core based on level information of outstanding requests, of the thread, for data blocks.

11. The method of claim 2 , wherein the step of adapting further comprises releasing pipeline resources allocated by the pipeline resources for a period which is based on a latency associated with the extracted cache level of the cache memory system.

12. The method of claim 1 , wherein the shared pipeline resources that are adaptively allocated based on the predicted latency include at least one of: physical registers, entries in a load queue, entries in a store queue, entries in a combined load/store queue, and entries in an issue queue.

13. The method of claim 12 , wherein the step of adapting, by the core, an allocation of shared pipeline resources associated with the pipeline which is processing the application based on the predicted latency further comprises:

reducing a number of physical registers which have been allocated by the pipeline to process the request for the data block.

14. A system comprising:

at least one processing core for executing an application; and

a cache memory system including a plurality of cache levels and a plurality of ways,

wherein the at least one processing core is configured to request a data block from the cache memory system,

wherein the cache memory system is configured to extract, from information stored in the cache memory system, a cache level and way in which the requested data block resides, from among the plurality of cache levels and plurality of ways of the cache memory system, and

wherein the at least one processing core and the cache memory system are configured such that, after the cache memory system extracts the cache level and way of the requested data block,

the cache memory system informs the at least one processing core of the extracted cache level,

the at least one processing core predicts a latency associated with retrieving the requested data block based on the extracted cache level, and

the at least one processing core adapts an allocation of shared resources associated with a pipeline which is processing the application based on the predicted latency.

15. The system of claim 14 , further comprising:

wherein the at least one processing core issues a memory request for the data block;

a location buffer which stores level information associated with the data block;

wherein, after receiving the memory request, the cache memory system finds an entry in a location buffer associated with the data block;

wherein the cache memory system finds, within the entry, information about a location where the data block currently resides; and

wherein the cache memory system sends the level information associated with the data block to the at least one processing core.

16. The system of claim 15 , wherein the at least one processing core determines whether a memory instruction associated with requesting the data block is a slow memory instruction based on whether a level of the cache memory system in which the location exists indicates a latency associated with providing the data block to the at least one processing core which is greater than a predetermined threshold.

17. The system of claim 16 , wherein the at least one processing core adapts processing of the application based on the location in the cache memory system by releasing already allocated pipeline resources allocated to the memory instruction, or instructions dependent on the memory instruction, if the memory instruction is determined to be a slow memory instruction.

18. The system of claim 16 , wherein the pipeline is capable of simultaneously executing instructions from at least two threads wherein the at least one processing core adapts processing of the application based on the location in the cache memory system by reprioritizing execution of threads in the pipeline associated with the application when a slow memory instruction is identified.

19. The system of claim 18 , wherein the reprioritization involves halting at least one of the threads for a period of time.

20. The system of claim 15 , wherein the at least one processing core is configured to adapt processing of the application based on the location of the cache memory system by delaying allocation of pipeline resources for a period which is based on a latency associated with the location in the cache memory system.

21. The system of claim 15 , wherein the pipeline is capable of simultaneously executing instructions from at least two threads and wherein the at least one processing core is configured to adapt processing of the application based on the location in the cache memory system by adjusting a priority of a thread in the pipeline being executed by the at least one processing core based on level information of outstanding requests, of the thread, for data blocks.

22. The system of claim 15 , wherein the at least one processing core adapts processing of the application based on the location in the cache memory system by releasing pipeline resources allocated by the pipeline resources for a period which is based on a latency associated with the extracted cache level of the cache memory system.

23. The system of claim 14 , wherein the shared pipeline resources that are adaptively allocated based on the predicted latency include at least one of: physical registers, entries in a load queue, entries in a store queue, entries in a combined load/store queue, and entries in an issue queue.

24. The system of claim 23 , wherein the adaptation, by the at least one processing core, of an allocation of shared pipeline resources associated with the pipeline which is processing the application based on the predicted latency further comprises:

reducing a number of physical registers which have been allocated by the pipeline to process the request for the data block.

25. A method for adapting application processing based on level information of a memory system, the method comprising:

requesting, by a core from the memory system, a data block,

wherein the memory system includes at least a level 1 cache and a level 2 cache, and at least a first-level cache location buffer accessed using virtual addresses, the first-level cache location buffer containing cache location entries, each cache location entry storing a virtual address tag, and a plurality of location information;

extracting, by the memory system from the location information stored in the first-level cache location buffer, a level of the memory system in which the data block resides;

wherein the extracted level of the memory system is capable of identifying a location of the requested data block as any one of,

the level 1 cache,

the level 2 cache, and

neither of the level 1 and level 2 caches;

informing the core of the extracted level of the memory system; and

adapting, by the core, an allocation of shared pipeline resources associated with a pipeline which is processing an application based on the extracted level of the memory system.

26. The method of claim 25 , further comprising:

in response to the extracted level identifying the location of the requested data block as the level 1 cache,

performing, by the memory system, a lookup operation for the requested data block at the level 1 cache without performing a lookup operation for the requested data block at the level 2 cache;

in response to the extracted level identifying the location of the requested data block as the level 2 cache,

performing, by the memory system, a lookup operation for the requested data block at the level 2 cache without performing a lookup operation for the requested data block at the level 1 cache; and

in response to the extracted level identifying the location of the requested data block as neither of the level 1 and level 2 caches,

performing, by the memory system, a lookup operation for the requested data block without performing a lookup operation for the requested data block at the level 1 cache and without performing a lookup operation for the requested data block at the level 2 cache.