Gate boosting transmission gate
A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.
1. A gate-boosting transmission gate comprising:
an input node;
an output node;
an n-channel transistor having a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold; and
a p-channel transistor having a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.
2. The gate-boosting transmission gate of claim 1 wherein:
the n-channel transistor has a threshold of about 0.25V; and
the p-channel transistor has a threshold of about 0.15V.
3. The gate-boosting transmission gate of claim 1 , further comprising:
a latch including a first inverter having an input and an output; and a second inverter having an input connected to the output of the first inverter and an output connected to the input of the first inverter; and
wherein the latch has complementary low and high output states, the high output state having a voltage level of about V DD +0.25V, and the low output state having a voltage level of about ground.
4. A gate-boosting transmission gate comprising:
an input node;
an output node;
an n-channel transistor having a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a voltage threshold of a first voltage; and
a p-channel transistor having a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a voltage threshold of a second voltage lower than the first voltage.
5. The gate-boosting transmission gate of claim 4 wherein:
the n-channel transistor has a threshold of about 0.25V; and
the p-channel transistor has a threshold of about 0.15V.
6. The gate-boosting transmission gate of claim 4 , further comprising:
a latch including a first inverter having an input and an output; and a second inverter having an input connected to the output of the first inverter and an output connected to the input of the first inverter; and
wherein the latch has complementary low and high output states, the high output state having a voltage level of about V DD +0.25V, and the low output state having a voltage level of about ground.