Strained FinFET source drain isolation
A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a second spacer simultaneously formed with a first spacer upon the sidewalls of a gate structure. The second spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the second spacer limits source and drain punch through to the SRB layer underneath a channel. An etch partially removes a SRB layer portion 24 within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The second spacer is formed by depositing spacer material with the fin void.
1. A semiconductor device fabrication method comprising:
epitaxially growing a Silicon Germanium (SiGe) strain relief buffer (SRB) layer upon a Silicon semiconductor substrate;
epitaxially growing a SiGe channel layer upon the SRB layer, wherein the SRB layer comprises a material having a lattice constant that is asymptotic to a lattice constant of the semiconductor substrate nearest the semiconductor substrate changing to a lattice constant that is asymptotic to a lattice constant of the channel layer nearest the channel layer;
removing portions of the SRB layer and portions of the channel layer to form a SRB layer portion upon the semiconductor substrate, to form a SRB fin portion integral to the SRB layer portion, and to form a fin upon the SRB fin portion aligned with the SRB fin portion;
forming a punch through stop (PTS) between the SRB fin portion and a top section of the fin by doping a lower section of the fin;
forming a shallow trench isolation (STI) layer upon respective upper surfaces of the SRB layer portion adjacent to the SRB fin portion and adjacent to the PTS;
forming a gate structure upon the STI layer around the PTS and the fin;
removing portions of the STI layer adjacent to the gate structure to form first STI portions upon the SRB layer portion adjacent to the gate structure and to form second STI portions under the gate structure, the removing portions of the STI layer exposing a segment of the SRB fin portion within a source region and a drain region (source and drain regions);
removing a portion of the SRB fin portion from a bottom surface of the PTS to a level below a top surface of the first STI portions forming a fin void;
forming a low-k spacer upon the gate structure sidewalls, upon the sidewalls of the second STI portions, and within the fin void by forming a low-k layer upon the gate structure sidewalls, upon the sidewalls of the second STI portions, upon the first STI portions, upon the PTS sidewalls, around the fin, and within the fin void, and subsequently removing portions of the low-k layer from the first STI portions, removing the low-k layer from the PTS sidewalls, and removing the low-k layer from the fin sidewalls and upper surface; and
epitaxially growing diamond-shaped volumes on the sidewalls of the fin within the source and drain regions.
2. The fabrication method of claim 1 , wherein the low-k spacer within the fin void limits source drain junction leakage.
3. The fabrication method of claim 1 , wherein the low-k spacer within the fin void limits source drain punch through to at least the SRB layer portion.
4. The fabrication method of claim 1 , further comprising:
removing the gate structure between the low-k spacer to form a replacement gate trench;
forming a high-k layer within the replacement gate trench by forming the high-k layer upon the low-k spacer, upon the second STI portions, upon the sidewalls of PTS, and upon the fin, and;
forming a replacement gate upon the high-k layer.
5. The fabrication method of claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer upon the first STI portions surrounding the diamond-shaped volumes.
6. The fabrication method of claim 1 , wherein the low-k spacer is formed by a material having a dielectric constant less than any dielectric constant of silicon dioxide.