Semiconductor device
View Patent ↗A semiconductor device ( 300 a ) comprising: a substrate ( 302 ) having a first surface ( 303 ); an n-type well ( 304 ) extending from the first surface ( 303 ) into the substrate ( 302 ) and configured to form a depletion region ( 306 ) in the substrate ( 302 ) around the n-type well ( 304 ); an insulating layer ( 340 ) extending over the first surface ( 303 ) of the substrate ( 302 ) from the n-type well ( 304 ), the insulating layer ( 340 ) configured to form an inversion layer ( 342 ) in the substrate ( 302 ) extending from the n-type well ( 304 ) adjacent to the first surface ( 303 ); wherein a p-type floating channel stopper ( 370 a ) is provided, configured to extend through the inversion layer ( 342 ) to reduce electrical coupling between the n-type well ( 304 ) and at least part of the inversion layer ( 342 ), and is electrically disconnected from a remainder of the substrate ( 320 ) outside of the depletion region ( 306 ).
1. A semiconductor device comprising:
a substrate having a first surface;
an n-type well extending from the first surface into the substrate and configured to form a depletion region in the substrate around the n-type well;
an insulating layer extending over the first surface of the substrate from the n-type well, the insulating layer configured to form an inversion layer in the substrate extending from the n-type well adjacent to the first surface; wherein
a p-type floating channel stopper is provided, configured to extend through the inversion layer to reduce electrical coupling between the n-type well and at least part of the inversion layer, and is electrically disconnected from a remainder of the substrate outside of the depletion region.
2. The semiconductor device of claim 1 , wherein the p-type floating channel stopper is in direct contact with the n-type well.
3. The semiconductor device of claim 1 , wherein the p-type floating channel stopper is separated from the n-type well.
4. The semiconductor device of any preceding claim, wherein the p-type floating channel stopper comprises a continuous structure surrounding the n-type well.
5. The semiconductor device of claim 1 , further comprising:
a plurality of n-type wells; and
a plurality of p-type floating channel stoppers;
wherein each p-type floating channel stopper is disposed between a respective pair of n-type wells.
6. The semiconductor device of claim 1 , further comprising a p-type well extending from the first surface of the substrate, the insulating layer configured to extend between the n-type well and the p-type well such that the inversion layer extends between the n-type well and the p-type well.
7. The semiconductor device of claim 6 , wherein, in use, the n-type well is configured to be coupled to a first positive voltage and the p-type well is configured to be coupled to a second negative voltage.
8. The semiconductor device of claim 7 , wherein, in use, the p-type well is configured to be coupled to electrical ground.
9. The semiconductor device of claim 6 , further comprising:
a plurality of n-type wells;
a plurality of p-type wells; and
a plurality of p-type floating channel stoppers;
wherein each p-type floating channel stopper is disposed between a respective n-type well and a respective p-type well.
10. The semiconductor device of claim 6 , wherein the p-type dopant concentration of the p-type well is greater than the p-type dopant concentration of the p-type floating channel stopper.
11. The semiconductor device of claim 1 , comprising:
a) a semiconductor controlled rectifier or thyristor;
b) a transistor;
c) a diode;
d) a diffused resistor.
12. The semiconductor device of claim 1 , wherein the p-type floating channel stopper is configured to split, electronically, the inversion layer into a first part connected to the n-type well and a second part disconnected from the n-type well.
13. The semiconductor device of claim 1 , wherein the remainder of the substrate outside of the depletion region is configured to be electrically grounded.
14. An electrostatic discharge protection device comprising the semiconductor device of claim 1 .
15. An electronic device comprising the electrostatic discharge protection device of claim 14 .
16. The semiconductor device of claim 1 , wherein the reduction in the electrical coupling between the n-type well and the inversion layer reduces a capacitance of the semiconductor device.
17. The semiconductor device of claim 1 , wherein a charge in the inversion layer is indirectly coupled to a charge in the n-type well via the n-type well.
18. The semiconductor device of claim 1 , wherein the reduction in the electrical coupling between the n-type well and the inversion layer reduces a capacitance of the semiconductor device without reducing Electrostatic Discharge (ESD) performance of the device.
19. The semiconductor device of claim 18 , wherein the capacitance of the device is below 250 fF and the semiconductor device has an ESD performance of above 15 kV.