Semiconductor device packages including a controller element
View Patent ↗Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. The controller element is operatively connected to the semiconductor memory devices of the stack through the redistribution substrate and the interposer substrate. Methods of manufacturing a semiconductor device package include positioning a redistribution substrate laterally adjacent to a controller element and attaching the redistribution substrate and the controller element to an interposer substrate. A stack of semiconductor memory devices is positioned over the controller element and the redistribution substrate. The controller element is operatively connected to the semiconductor memory devices of the stack through the redistribution substrate and the interposer substrate.
1. A semiconductor device package, comprising:
a stack of semiconductor memory devices positioned over an interposer substrate;
a controller element positioned directly between the stack of semiconductor memory devices and the interposer substrate; and
a redistribution substrate positioned laterally adjacent to the controller element,
wherein the controller element is operatively connected to the semiconductor memory devices of the stack through the redistribution substrate and the interposer substrate.
2. The semiconductor device package of claim 1 , wherein the redistribution substrate laterally surrounds the controller element.
3. The semiconductor device package of claim 1 , wherein the redistribution substrate comprises a through hole, and the controller element is positioned within the through hole.
4. The semiconductor device package of claim 1 , wherein a thickness of the redistribution substrate is substantially the same as a thickness of the controller element.
5. The semiconductor device package of claim 1 , wherein the semiconductor memory devices of the stack comprise non-volatile memory devices, and the semiconductor device package further comprises at least one volatile memory device.
6. The semiconductor device package of claim 5 , wherein at least a portion of the at least one volatile memory device is positioned directly between the interposer substrate and the non-volatile memory devices.
7. The semiconductor device package of claim 6 , wherein the at least one volatile memory device is positioned laterally adjacent to the controller element.
8. The semiconductor device package of claim 6 , wherein at least a portion of the at least one volatile memory device is positioned directly between the interposer substrate and the controller element.
9. The semiconductor device package of claim 6 , wherein the at least one volatile memory device comprises a first volatile memory device and a second volatile memory device.
10. The semiconductor device package of claim 9 , wherein the second volatile memory device is positioned on top of the non-volatile memory devices.
11. The semiconductor device package of claim 1 , further comprising at least one capacitor operatively connected to the controller element through the interposer substrate and the redistribution substrate.
12. A semiconductor device package, comprising:
an interposer substrate;
a controller element over the interposer substrate;
semiconductor memory devices stacked over the controller element, such that at least a portion of the controller element is positioned directly between the semiconductor memory devices and the interposer substrate;
a redistribution substrate laterally adjacent to the controller element, at least a portion of the redistribution substrate being positioned directly between the interposer substrate and the semiconductor memory devices;
inner wire bonds electrically connecting bond pads of the controller element with respective first bond pads of the redistribution substrate; and
outer wire bonds electrically connecting bond pads of the interposer substrate with respective second bond pads of the redistribution substrate, the first bond pads of the redistribution substrate being respectively electrically connected to the second bond pads of the redistribution substrate.
13. The semiconductor device package of claim 12 , wherein the redistribution substrate has an outer peripheral size and shape that is substantially the same as an outer peripheral size and shape of at least one semiconductor memory device of the stack.
14. The semiconductor device package of claim 12 , wherein the second bond pads of the redistribution substrate have a pitch that is greater than a pitch of the bond pads of the controller element.
15. The semiconductor device package of claim 12 , further comprising memory access wire bonds electrically connecting additional bond pads of the interposer substrate with respective memory bond pads of the semiconductor memory devices, wherein the bond pads of the interposer substrate to which the outer wire bonds are electrically connected are positioned in a region of the interposer substrate proximate a first lateral edge of the interposer substrate and the additional bond pads of the interposer substrate to which the memory access wire bonds are electrically connected are positioned in a region of the interposer substrate proximate a second, opposite lateral edge of the interposer substrate.
16. The semiconductor device package of claim 15 , wherein the semiconductor memory devices are stacked to be laterally offset from one another in a single direction, and the memory bond pads of the semiconductor memory devices are along a common lateral side of each respective semiconductor memory device of the semiconductor memory devices.