Computer implemented system and method of identification of useful untested states of an electronic design
A computer implemented system and method of identification of useful untested states of an electronic design, comprising, parsing at least one netlist of a representation of the electronic design comprised at least in part of at least one analog portion, determining at least one instrumentation point based on the at least one netlist, generating at least one instrumented netlist based on the at least one instrumentation point and determining an analog verification coverage utilizing the at least one instrumented netlist.
1. A computer implemented method of instrumentation of an electronic design, comprising:
receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, at least one digital portion and at least one analog portion;
generating at least one instrumented netlist based at least in part upon said representation of said electronic design;
receiving at least one specification of said electronic design;
generating at least one set of valid states based on said at least one specification;
receiving at least one verification coverage history of said electronic design;
correlating said at least one verification coverage history and at least one input vector; and
assessing completeness of verification based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.
2. The computer implemented method of instrumentation of said electronic design of claim 1 , further comprising determining a minimum number of said at least one input vector to maximize said assessing completeness of verification.
3. The computer implemented method of instrumentation of said electronic design of claim 2 , further comprising simulating at a behavioral level of said representation of said electronic design said minimum number of said at least one input vector.
4. The computer implemented method of instrumentation of said electronic design of claim 3 , further comprising assessing a measurement output at said behavioral level simulation, wherein said assessment is based at least in part upon said at least one set of valid states.
5. The computer implemented method of instrumentation of said electronic design of claim 4 , further comprising simulating at a transistor level of said representation of said electronic design said minimum number of said at least one input vector.
6. The computer implemented method of instrumentation of said electronic design of claim 5 , further comprising correlating said measurement output at said transistor level simulation, wherein said correlation is based at least in part upon said measurement output at said behavioral level simulation.
7. A computer program embodied on a non-transitory computer useable medium, said non-transitory computer usable medium having stored thereon a sequence of instructions which, when executed by a processor causes a computer to execute a method of instrumentation of an electronic design, comprising the steps of:
receiving by said computer a computer readable representation of said electronic design having at least in one part of said electronic design, at least one digital portion and at least one analog portion;
generating at least one instrumented netlist based at least in part upon said representation of said electronic design;
receiving at least one specification of said electronic design;
generating at least one set of valid states based on said at least one specification;
receiving at least one verification coverage history of said electronic design;
correlating said at least one verification coverage history and at least one input vector; and
assessing completeness of verification based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.
8. The computer product of claim 7 , further comprising determining a minimum number of said at least one input vector to maximize said assessing completeness of verification.
9. The computer product of claim 8 , further comprising simulating at a behavioral level of said representation of said electronic design said minimum number of said at least one input vector.
10. The computer product of claim 9 , further comprising assessing a measurement output at said behavioral level simulation, wherein said assessment is based at least in part upon said at least one set of valid states.
11. The computer product of claim 10 , further comprising simulating at a transistor level of said representation of said electronic design said minimum number of said at least one input vector.
12. The computer product of claim 11 , further comprising correlating said measurement output at said transistor level simulation, wherein said correlation is based at least in part upon said measurement output at said behavioral level simulation.