Apparatus and method for measuring power supply noise
Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.
1. An apparatus comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and
an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN;
an on-die power supply noise (PSN) sampler to sample the power supply with the injected noise, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and
a phase noise accumulator to randomize periods of the at least two different clock signals, wherein the phase noise accumulator comprises:
a phase provider to provide phase signals; and
a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals.
2. The apparatus of claim 1 , wherein the phase selection multiplexer is
a glitch-free phase selection multiplexer.
3. The apparatus of claim 2 , wherein the phase provider comprises a delay line with a plurality of delay elements to provide phase signals for the glitch-free phase selection multiplexer.
4. The apparatus of claim 2 comprises a pseudorandom binary sequence (PRBS) generator coupled to the phase provider.
5. The apparatus of claim 4 , wherein the PRBS generator is a phase noise source.
6. The apparatus of claim 4 , wherein the PRBS generator is to generate signals for controlling the glitch-free phase selection multiplexer.
7. The apparatus of claim 4 comprises at least two digital accumulators coupled to the PRBS generator, wherein the at least two digital accumulators are to generate two selection signals for controlling the glitch-free phase selection multiplexer.
8. The apparatus of claim 1 , wherein the phase noise accumulator is to adjust a phase difference between the at least two different clock signals.
9. The apparatus of claim 1 , wherein the on-die synchronous power supply noise injector is operable to inject a step noise to the power supply.
10. The apparatus of claim 9 comprises logic which is operable to differentiate a response of the step noise to generate an impulse response.
11. The apparatus of claim 10 comprises logic which is operable to perform discrete Fourier transform of the impulse response to generate an impedance profile of the PDN.
12. An apparatus comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit;
an on-die power supply noise (PSN) sampler to sample the power supply with noise injected thereto, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and
a phase noise accumulator to randomize the periods of the at least two different clock signals, wherein the phase noise accumulator comprises:
a phase provider to provide phase signals; and
a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals.
13. The apparatus of claim 12 comprises an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN.
14. The apparatus of claim 13 , wherein the on-die synchronous power supply noise injector is operable to inject a step noise to the power supply.
15. The apparatus of claim 14 comprises:
logic which is operable to differentiate a response of the step noise to generate an impulse response; and
logic which is operable to perform discrete Fourier transform of the impulse response to generate an impedance profile of the PDN.
16. A system comprising:
a memory;
a processor coupled to the memory, the processor comprising:
a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and
an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN;
an on-die power supply noise (PSN) sampler to sample the power supply with the injected noise, wherein the PSN sampler is to sample the power supply with at least two different clock signals; and
a phase noise accumulator to randomize periods of the at least two different clock signals, wherein the phase noise accumulator comprises:
a phase provider to provide phase signals; and
a phase selection multiplexer to receive the phase signals and to provide signals for generating the at least two different clock signals; and
a wireless interface for allowing the processor to communicate with another device.
17. The apparatus of claim 1 , wherein the on-die synchronous power supply noise injector comprises a digital-to-analog converter (DAC).
18. The apparatus of claim 17 , wherein the DAC is combined with a pattern generator.
19. The apparatus of claim 1 , wherein the on-die synchronous power supply noise injector is to receive an amplitude control signal to control an amplitude of the injected noise on the PDN.
20. The apparatus of claim 1 comprises a synchronization switch to synchronize an injected clock, which is to be received by the on-die synchronous power supply noise injector, and an input clock which is to be received by a phase rotator coupled to the phase noise accumulator.
21. The apparatus of claim 1 , wherein the on-die PSN sampler includes two oscillator based analog-to-digital converters (ADCs).